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公开(公告)号：DE69033007T2
公开(公告)日：1999-10-07
申请号：DE69033007
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS , KACZMARCZYK JOHN , BUCHHOLZ DALE , WHITE RICHARD , CHANG HUNGKUN , NOLAN MICHAEL
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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公开(公告)号：DE69013327T2
公开(公告)日：1995-05-11
申请号：DE69013327
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD , BUCHHOLZ DALE , JOHANSON LISA , FREEBURG THOMAS
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：DE69013327D1
公开(公告)日：1994-11-17
申请号：DE69013327
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD , BUCHHOLZ DALE , JOHANSON LISA , FREEBURG THOMAS
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：DE69033007D1
公开(公告)日：1999-04-22
申请号：DE69033007
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS , KACZMARCZYK JOHN , BUCHHOLZ DALE , WHITE RICHARD , CHANG HUNGKUN , NOLAN MICHAEL
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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