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公开(公告)号：DE69032502D1
公开(公告)日：1998-08-27
申请号：DE69032502
申请日：1990-11-27
Applicant: MOTOROLA INC
Inventor： BERKEN JAMES , FREEBURG THOMAS , OGASAWARA ROY , WHITE RICHARD , MITZLAFF JAMES , BEDLEK GREGORY
Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.
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公开(公告)号：DE69013327T2
公开(公告)日：1995-05-11
申请号：DE69013327
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD , BUCHHOLZ DALE , JOHANSON LISA , FREEBURG THOMAS
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：DE69032502T2
公开(公告)日：1999-03-04
申请号：DE69032502
申请日：1990-11-27
Applicant: MOTOROLA INC
Inventor： BERKEN JAMES , FREEBURG THOMAS , OGASAWARA ROY , WHITE RICHARD , MITZLAFF JAMES , BEDLEK GREGORY
Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.
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公开(公告)号：DE69013327D1
公开(公告)日：1994-11-17
申请号：DE69013327
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD , BUCHHOLZ DALE , JOHANSON LISA , FREEBURG THOMAS
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：WO03009395A3
公开(公告)日：2003-09-18
申请号：PCT/US0214366
申请日：2002-05-06
Applicant: MOTOROLA INC
Inventor： EISENBEISER KURT W , FREEBURG THOMAS , PRENDERGAST JAMES E , OOMS WILLIAM J , DROOPAD RAVINDRANATH , RAMDANI JAMAL
IPC: H01L21/20 , H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/0687 , H01L31/0693 , H01L31/18 , H01L31/068
CPC classification number: H01L31/0693 , H01L21/02378 , H01L21/02381 , H01L21/02395 , H01L21/02488 , H01L21/02543 , H01L21/02546 , H01L21/02551 , H01L21/31691 , H01L21/8221 , H01L23/66 , H01L31/0687 , H01L2924/0002 , Y02E10/544 , H01L2924/00
Abstract: Multijunction solar cell structures (100) including high quality epitaxial layers of monocrystalline semiconductor materials that are grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers are disclosed. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (104) on a silicon wafer. The accommodating buffer (104) layer is a layer of monocrystalline material spaced apart from the silicon wafer by an amorphous interface layer (112) of silicon oxide. The amorphous interface layer (112) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Multiple and varied accommodating buffer layers can be used to achieve the monolithic integration of multiple non-lattice matched solar cell junctions (302, 304).
Abstract translation: 公开了包括通过形成用于生长单晶层的柔性衬底生长在单晶衬底（102）如大硅晶片上的单质半导体材料的高质量外延层的多结太阳能电池结构（100）。 实现顺应性衬底的形成的一种方法包括首先在硅晶片上生长容纳缓冲层（104）。 容纳缓冲器（104）层是通过氧化硅的非晶界面层（112）与硅晶片间隔开的单晶材料层。 非晶界面层（112）耗散应变并允许高质量单晶氧化物容纳缓冲层的生长。 可以使用多个不同的容纳缓冲层来实现多个非晶格匹配的太阳能电池结的单片集成（302,304）。
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Patent Agency Ranking
公开(公告)号：DE69033007T2
公开(公告)日：1999-10-07
申请号：DE69033007
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS , KACZMARCZYK JOHN , BUCHHOLZ DALE , WHITE RICHARD , CHANG HUNGKUN , NOLAN MICHAEL
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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公开(公告)号：DE69129938T2
公开(公告)日：1999-03-11
申请号：DE69129938
申请日：1991-03-01
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS
Abstract: There is provided a mechanism for networking satellite and terrestrial networks. It comprises: maintaining subscriber-received power levels of terrestrial network transmissions about one order of magnitude above co-channel satellite transmissions to overcome interference and maintaining subscriber transmissions to terrestrial networks at power levels about one order of magnitude of the below co-channel transmissions to satellite networks to avoid causing interference at the satellite. Such power level maintenance is provided by the network in communication with such subscriber. Moreover, a non-orbiting ("grounded") satellite cooperates as a switching node of both the satellite network and a terrestrial network to relay information between a terrestrial subscriber and the satellite radiotelephone network over a terrestrial network. The terrestrial network and the satellite network may communicate via either the inter-satellite spectrum or the terrestrial-to-satellite spectrum.
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公开(公告)号：DE69119844T2
公开(公告)日：1996-11-28
申请号：DE69119844
申请日：1991-02-25
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS , WHITE RICHARD
Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
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公开(公告)号：DE3473106D1
公开(公告)日：1988-09-01
申请号：DE3473106
申请日：1984-06-28
Applicant: MOTOROLA INC
Inventor： KREBS JAY , FREEBURG THOMAS
Abstract: A data communications system is described in which variable length messages are communicated between a general communications controller (GCC) and a plurality of portable and mobile radios. The variable length messages include a bit synchronization field, a message synchronization field and a plurality of channel data blocks for efficiently and reliably handling long strings of data or text. Each channel data block includes an information field, a parity field for error-connecting the information field and a channel state field indicating whether or not the radio channel is busy or free. The GCC is coupled to a cellular arrangement of channel communications modules (CCM's), which each include a radio transmitter and/or radio receiver. The mobile and portable radios communicate with the GCC by way of the CCM's.
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公开(公告)号：DE3278848D1
公开(公告)日：1988-09-01
申请号：DE3278848
申请日：1982-11-12
Applicant: MOTOROLA INC
Inventor： MILLEKER WILLIAM , FREEBURG THOMAS , STEPIEN MICHAEL
Abstract: Data muting apparatus is described that mutes variable-length data signals communicated between a central station and mobile and portable radios in a dispatch radio communications system. The central station includes a base station transceiver, a dispatcher console, a general communications controller (GCC), a digital communications computer and a display terminal. The base station transmitter and receiver communicate over an RF duplex channel to the transceiver of the mobile and portable radios. The dispatcher console provides for voice communications and is coupled by a transmit signal line and a receive signal line to the base station transceiver. The GCC provides for data communications and is also coupled to the transmit signal line and is interposed between the dispatcher console and the base station transceiver in the receive signal line. The GCC and mobile and portable radios include data muting apparatus enbodying the present invention. The data muting apparatus includes a detector for detecting the presence of a carrier signal and muting circuitry for muting the transceiver output for a predetermined time interval when a carrier signal has been detected. During the predetermined time interval, other circuitry may detect a synchronization word in a received data signal and mute the receiver output until still other circuitry detects the last bit of a following information word in the received data signal and unmutes the transceiver output. Thus, data signals at the beginning of each communication are muted without impairing voice communications.
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