公开(公告)号：DE69208297D1

公开(公告)日：1996-03-28

申请号：DE69208297

申请日：1992-07-13

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F ,  DAVIES ROBERT B

IPC: H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812

Abstract: A semiconductor device having a channel region having a first and a second portion (13a, 13b). The first and second portions of the channel region (13a, 13b) are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

公开(公告)号：DE4118593C2

公开(公告)日：2001-04-05

申请号：DE4118593

申请日：1991-06-06

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F ,  LIAW H MING ,  TOMOZANE MAMORU

IPC: H01L21/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/76 ,  H01L21/8258 ,  H01L21/82 ,  H01L21/84 ,  H01L21/306

Abstract: Silicon and non-silicon semiconductor devices are fabricated on a single chip by bonding a silicon wafer to a non-silicon semiconductor substate. Portions of the non-silicon semiconductor substrate are selectively etched to expose the silicon wafer. Semiconductor devices may then be formed in the silicon wafer and on the non-silicon semiconductor substrate. Alternatively, selective epitaxial silicon may be grown where the non-silicon semiconductor substrate was removed. In another embodiment, a non-silicon semiconductor substrate having wells formed therein is bonded to a silicon wafer. The non-silicon semiconductor substrate is then polished until openings are provided to the silicon wafer. Further processing is carried out as described above.

公开(公告)号：DE69208297T2

公开(公告)日：1996-09-05

申请号：DE69208297

申请日：1992-07-13

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F ,  DAVIES ROBERT B

IPC: H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812

Abstract: A semiconductor device having a channel region having a first and a second portion (13a, 13b). The first and second portions of the channel region (13a, 13b) are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

公开(公告)号：DE68923730T2

公开(公告)日：1996-04-04

申请号：DE68923730

申请日：1989-04-20

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L21/76 ,  H01L29/72

Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy (12,13,14) on top of a substrate (10). The first epitaxial layer (12) is of the same conductivity type as the substrate (10) and adds additional height to the substrate (10) surrounding the buried layer (11). The buried layer (11) serves as a collector and it is surrounded by an isolation area (24). The top two epitaxial layers (13,14) are of a conductivity type opposite to that of the substrate (10) with the upper most epitaxial layer (14) having a higher dopant density than does the middle epitaxial layer (13). A master mask is used to provide self-alignment between the isolation area (24), a collector plug (28) which makes contact to the buried layer (11), and a base region (29).

公开(公告)号：DE68923730D1

公开(公告)日：1995-09-14

申请号：DE68923730

申请日：1989-04-20

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L21/76 ,  H01L29/72

Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy (12,13,14) on top of a substrate (10). The first epitaxial layer (12) is of the same conductivity type as the substrate (10) and adds additional height to the substrate (10) surrounding the buried layer (11). The buried layer (11) serves as a collector and it is surrounded by an isolation area (24). The top two epitaxial layers (13,14) are of a conductivity type opposite to that of the substrate (10) with the upper most epitaxial layer (14) having a higher dopant density than does the middle epitaxial layer (13). A master mask is used to provide self-alignment between the isolation area (24), a collector plug (28) which makes contact to the buried layer (11), and a base region (29).

公开(公告)号：DE4118593A1

公开(公告)日：1992-03-05

申请号：DE4118593

申请日：1991-06-06

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F ,  LIAW H MING ,  TOMOZANE MAMORU

IPC: H01L21/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/76 ,  H01L21/8258

Abstract: Silicon and non-silicon semiconductor devices are fabricated on a single chip by bonding a silicon wafer to a non-silicon semiconductor substate. Portions of the non-silicon semiconductor substrate are selectively etched to expose the silicon wafer. Semiconductor devices may then be formed in the silicon wafer and on the non-silicon semiconductor substrate. Alternatively, selective epitaxial silicon may be grown where the non-silicon semiconductor substrate was removed. In another embodiment, a non-silicon semiconductor substrate having wells formed therein is bonded to a silicon wafer. The non-silicon semiconductor substrate is then polished until openings are provided to the silicon wafer. Further processing is carried out as described above.