公开(公告)号：AU5371401A

公开(公告)日：2001-11-12

申请号：AU5371401

申请日：2001-04-20

Applicant: MOTOROLA INC WARE

Inventor： COSTA JULIO ,  SCHIRMANN ERNEST ,  CODY NYLES W ,  MARTINEZ MARINO J

IPC: H01L29/423 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/41 ,  H01L29/47 ,  H01L29/812 ,  H01L29/872

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

公开(公告)号：AU5157201A

公开(公告)日：2001-11-12

申请号：AU5157201

申请日：2001-04-11

Applicant: MOTOROLA INC

Inventor： HUANG JENN-HWA ,  GLASS ELIZABETH C ,  HARTIN OLIN ,  VALENTINE WENDY L ,  COSTA JULIO

IPC: H01L29/872 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/02 ,  H01L27/06 ,  H01L27/095 ,  H01L29/47 ,  H03F1/30 ,  H03K17/14 ,  H03K19/003

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

公开(公告)号：WO0184616A3

公开(公告)日：2002-02-21

申请号：PCT/US0112824

申请日：2001-04-20

Applicant: MOTOROLA INC

Inventor： COSTA JULIO ,  SCHIRMANN ERNEST ,  CODY NYLES W ,  MARTINEZ MARINO J

IPC: H01L29/423 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/41 ,  H01L29/47 ,  H01L29/812 ,  H01L29/872 ,  H01L29/76

CPC classification number: H01L29/66871 ,  H01L21/28587 ,  H01L29/475 ,  H01L29/66462

Abstract: An enhancement mode semiconductor device has a barrier layer (102) disposed between the gate electrode (104) of the device and the semiconductor substrate (106) underlying the gate electrode (104). The barrier layer (102) increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate (106) underlying the gate electrode (104) operates in an enhancement mode. The barrier layer (102) is particularly useful in compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract translation: 增强型半导体器件具有设置在器件的栅电极（104）与栅电极（104）下方的半导体衬底（106）之间的阻挡层（102）。 阻挡层（102）增加了栅电极 - 阻挡层 - 衬底界面的肖特基势垒高度，使得栅电极（104）下面的衬底（106）的部分以增强模式工作。 阻挡层（102）在化合物半导体场效应晶体管中特别有用，并且阻挡层的优选材料包括砷化铝镓和砷化铟镓。