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公开(公告)号：US3558910A
公开(公告)日：1971-01-26
申请号：US3558910D
申请日：1968-07-19
Applicant: MOTOROLA INC
Inventor： DALE ROBERT G , FAY GARY V
IPC: H01H9/54 , H03K17/725 , H01H33/59
CPC classification number: H01H9/542 , H03K17/725 , Y10T307/911
Abstract: Disclosed is circuitry for controlling the flow of current from an AC source to a load and includes a bilateral semiconductor switch such as a semiconductor triac connected in parallel with the contacts of an electromechanical relay. The relay and triac are connected in series with the AC source and the load. Circuit means are connected between a gate electrode of the triac and circuit input terminals to which the AC source is connected and provides turn-on gate current for the triac prior to and during the closure of the electromechanical relay contacts to prevent effects of contact bounce. This circuit means also provides a sustaining or hold current to the triac subsequent to the opening of the relay contacts and thereby prevents contact arcing. The triac conducts before the relay contacts close and after the relay contacts open.
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Patent Agency Ranking
公开(公告)号：DE3275422D1
公开(公告)日：1987-03-12
申请号：DE3275422
申请日：1982-05-03
Applicant: MOTOROLA INC
Inventor： FAY GARY V , PSHAENICH ALVIN
Abstract: A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
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公开(公告)号：IT8248503D0
公开(公告)日：1982-05-25
申请号：IT4850382
申请日：1982-05-25
Applicant: MOTOROLA INC
Inventor： FAY GARY V , PSHAENICH ALVIN
Abstract: A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
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公开(公告)号：IT1148933B
公开(公告)日：1986-12-03
申请号：IT4850382
申请日：1982-05-25
Applicant: MOTOROLA INC
Inventor： FAY GARY V , PSHAENICH ALVIN
Abstract: A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
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公开(公告)号：WO1982004349A1
公开(公告)日：1982-12-09
申请号：PCT/US1982000591
申请日：1982-05-03
Applicant: MOTOROLA INC
Inventor： MOTOROLA INC , FAY GARY V , PSHAENICH ALVIN
IPC: H01H47/32
Abstract: Appareil a commutateur de regulation et de commutation de courant ou un transistor de puissance a mode d'enrichissement de semiconducteur a oxyde metallique a N canaux NMOS est utilise dans le conducteur positif pour reguler le flux de courant s'ecoulant d'une source de puissance a une charge. Afin d'obtenir un etat de commutation 'on' de faible resistance pour le transistor de puissance NMOS, la porte de commande doit etre polarisee sur une tension qui depasse la tension positive de la source de puissance. Cette tension de polarisation est generee dans l'appareil.
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公开(公告)号：EP0079937A4
公开(公告)日：1984-09-06
申请号：EP82902002
申请日：1982-05-03
Applicant: MOTOROLA INC
Inventor： FAY GARY V , PSHAENICH ALVIN
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