Abstract:
This accessing circuitry allows conventional multiplexing techniques to be used in a system with a liquid crystal display having a plurality of digits, each digit having a plurality of segments and a back plane. The circuitry includes a source of information to be supplied to the array. A plurality of enabling gates is provided, one for each segment and one for the back plane for each digit of the liquid crystal display. A decoder/driver is connected between the source of information and the enabling gates for the segments of the liquid crystal display. Means is provided for supplying drive signals and control pulses to the enabling gates, whereby signals equal but opposite in polarity are applied to selected ones of the segments and their back planes and signals of the same polarity and magnitude are supplied to unselected segments and their back planes. This circuitry allows multiplexing of liquid crystal displays without supplying any direct current (DC) signal component to the liquid crystal cells of the display, thus avoiding degradation of the cells.
Abstract:
A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
Abstract:
A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
Abstract:
A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
Abstract:
Appareil a commutateur de regulation et de commutation de courant ou un transistor de puissance a mode d'enrichissement de semiconducteur a oxyde metallique a N canaux NMOS est utilise dans le conducteur positif pour reguler le flux de courant s'ecoulant d'une source de puissance a une charge. Afin d'obtenir un etat de commutation 'on' de faible resistance pour le transistor de puissance NMOS, la porte de commande doit etre polarisee sur une tension qui depasse la tension positive de la source de puissance. Cette tension de polarisation est generee dans l'appareil.