公开(公告)号：JPH1055331A

公开(公告)日：1998-02-24

申请号：JP9457097

申请日：1997-03-28

Applicant: MOTOROLA INC

Inventor： CIRCELLO JOSEPH C ,  GAY JAMES G ,  GLOVER CLINTON T ,  TRAYNOR KEVIN M

IPC: G06F13/14 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To secure a proper interface between a processor and an external device by defining a value of a read/write access signal that is outputted to a system bus from a system bus controller as a function of a designated address space. SOLUTION: A processor (CPU) 101 is connected to N pieces of external devices 111 to 113 via a system bus 107 that serves as an interface having no adhesive. A processor core 102 of the CPU 101 is connected to an SBC (system bus controller) 103 via an address bus 104, a data bus 105 and a control bus 106. In regard to the CPU 101, the devices 111 to 113 are located in an address space where the read/write accesses are executable. Then a system engineer generates a program command to make the SBC 103 produce an ERE signal value never that is needed by the external devices (address space).

公开(公告)号：IE970147A1

公开(公告)日：1997-10-08

申请号：IE970147

申请日：1997-03-03

Applicant: MOTOROLA INC

Inventor： CIRCELLO JOSEPH C ,  GAY JAMES G ,  GLOVER CLINTON T ,  TRAYNOR KEVIN M

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

Abstract: A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112,113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111,112,113). .

公开(公告)号：SG64973A1

公开(公告)日：1999-05-25

申请号：SG1997000848

申请日：1997-03-19

Applicant: MOTOROLA INC

Inventor： CIRCELLO JOSEPH C ,  GAY JAMES G ,  GLOVER CLINTON T ,  TRAYNOR KEVIN M

IPC: G06F13/14 ,  G06F13/16

Abstract: A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).