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公开(公告)号：JPH1055331A
公开(公告)日：1998-02-24
申请号：JP9457097
申请日：1997-03-28
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , GAY JAMES G , GLOVER CLINTON T , TRAYNOR KEVIN M
Abstract: PROBLEM TO BE SOLVED: To secure a proper interface between a processor and an external device by defining a value of a read/write access signal that is outputted to a system bus from a system bus controller as a function of a designated address space. SOLUTION: A processor (CPU) 101 is connected to N pieces of external devices 111 to 113 via a system bus 107 that serves as an interface having no adhesive. A processor core 102 of the CPU 101 is connected to an SBC (system bus controller) 103 via an address bus 104, a data bus 105 and a control bus 106. In regard to the CPU 101, the devices 111 to 113 are located in an address space where the read/write accesses are executable. Then a system engineer generates a program command to make the SBC 103 produce an ERE signal value never that is needed by the external devices (address space).
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公开(公告)号：JPH1083305A
公开(公告)日：1998-03-31
申请号：JP11344297
申请日：1997-04-14
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , GOKINGCO JEFFERSON
Abstract: PROBLEM TO BE SOLVED: To allow a data processing system to correctly process all the exceptions and to restore a primary state after then by making optional the hardware support for the erroneous matching of an operand. SOLUTION: When a supervisor and hardware support for the erroneous matching of user stack operation are optical, a data processor 3 records stack operation and incorporates a single stack pointer. Since this pointer automatically matches with a 0-modulo-4 address which is lower than present address setting and closet to it, a system error is not generated even without hardware support for the erroneously matching operand. When automatic matching is executed, the data processor 3 stores a format field in an exception stack frame and gives information on a stack pointer at the time of an error. When an exception is processed, the processor 3 restores the stack pointer to the primary value.
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公开(公告)号：JP2003108435A
公开(公告)日：2003-04-11
申请号：JP2002277789
申请日：2002-09-24
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , MCCARTHY DANIEL M , CLOETENS HENRI , WOO NANCY H , HOOSER BRIDGET C
Abstract: PROBLEM TO BE SOLVED: To optimize system memory addressing in an information processing. SOLUTION: This system 10 provides an addressing mode settable by users according to control information included in an input address. By using coding control information stored in an address replacement control resister (70 to 72) set by the plurality of users, specified bits of the input address are replaced, and it is judged whether what bit value must be used to selectively generate a corresponding replacement address. Since the pipeline of a processor need not be changed, various types of replacement addressing modes can be defined by the users, and executed by using either of a general processor and a dedicated processor.
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公开(公告)号：DE69616463T2
公开(公告)日：2002-05-23
申请号：DE69616463
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , HOHL WILLIAM A
Abstract: A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.
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公开(公告)号：DE69616708D1
公开(公告)日：2001-12-13
申请号：DE69616708
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C
Abstract: A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset exception processing routine. If an external breakpoint signal, BKPT is asserted during a quiescent time by external development system (7), data processor (3) downloads a target memory value into a memory (6) such that any hardware register configuration may be performed.
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Patent Agency Ranking
公开(公告)号：SG64973A1
公开(公告)日：1999-05-25
申请号：SG1997000848
申请日：1997-03-19
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , GAY JAMES G , GLOVER CLINTON T , TRAYNOR KEVIN M
Abstract: A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).
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公开(公告)号：DE69616462T2
公开(公告)日：2002-05-23
申请号：DE69616462
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , RIEDEL KLAUS R
Abstract: A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
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公开(公告)号：IE970146A1
公开(公告)日：1997-10-22
申请号：IE970146
申请日：1997-03-03
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , GOKINGCO JEFFERSON
Abstract: A data processor (3) implements a single system stack pointer (244) to create records of both supervisor and user stack operations when hardware support for misalignment of such stack operations is optional. The single system stack pointer is implemented as a self-aligning stack pointer which automatically aligns itself to a nearest O-modulo-4 address below a current address setting such that no alignment system errors occur even when there is no hardware support for misaligned operands. Once the automatic alignment has occurred, the data processor stores a format field in an exception stack frame to indicate information about the alignment of the stack pointer at the time of the error. When the exception has been serviced, the processor uses the four bit format field stored in the exception stack frame to restore the stack pointer to its original value at the time of the exception.
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公开(公告)号：DE69616708T2
公开(公告)日：2002-08-01
申请号：DE69616708
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C
Abstract: A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset exception processing routine. If an external breakpoint signal, BKPT is asserted during a quiescent time by external development system (7), data processor (3) downloads a target memory value into a memory (6) such that any hardware register configuration may be performed.
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公开(公告)号：DE69616463D1
公开(公告)日：2001-12-06
申请号：DE69616463
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , HOHL WILLIAM A
Abstract: A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.
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