公开(公告)号：JPH10303802A

公开(公告)日：1998-11-13

申请号：JP12168998

申请日：1998-04-15

Applicant: MOTOROLA INC

Inventor： HIETALA ALEXANDER WAYNE ,  OBERHAUSER THOMAS EDWARD

IPC: H04B7/26 ,  H04B1/16 ,  H04W52/02

Abstract: PROBLEM TO BE SOLVED: To save power consumption as much as possible by providing a constitution where a device and a controller are connected to each other via 1st and 2nd communication lines of different capacities, the 1st communication line is sometimes set in a disable state and a communication controller can periodically turn off the power supply of a communication device and reset it in a power-on state. SOLUTION: A communication system 100 consists of a remote communication device 101 and a local communication device 102. In a standby state of the control mode of the device 102, a control part 106 and an RF part 105 are partly set in a power-down or power-off state. Thereby, a regulator control line 150 and a control line 117 are applied. Thus, the registers 140 and 141 and an RF transceiver IC 109 including a master clock 112 can be periodically set in a power-off state respectively. Then the power consumption is saved without affecting the operation of the device 102.

公开(公告)号：GB2396067A

公开(公告)日：2004-06-09

申请号：GB0327505

申请日：2002-04-18

Applicant: MOTOROLA INC

Inventor： SCHWENT DALE GERARD ,  HIETALA ALEXANDER WAYNE

IPC: H03G1/00 ,  H03G3/20 ,  H03G3/30 ,  H03F3/189 ,  H04B1/04 ,  H04L27/20 ,  H04L27/36 ,  H04L27/04 ,  H03F3/38 ,  H04K1/02

Abstract: RF amplifier control circuits for transmitters in mobile communication devices, combinations thereof and methods therefor. The control circuits include generally proportional and integral control circuits having an output coupled to a control input of an amplifier (110). An initial control signal is applied to the amplifier before a vector modulator output (120) coupled an input thereof is at full output power. The vector modulator output is ramped to full output after applying the initial control signal. Thereafter, the initial control signal applied to the amplifier during ramping is corrected by integrating an output of the amplifier relative to a second reference signal with an integral control circuit coupled to the control input of the amplifier, the second reference signal is proportional to the ramping vector modulator output.

公开(公告)号：SG72729A1

公开(公告)日：2000-05-23

申请号：SG1997000470

申请日：1997-02-25

Applicant: MOTOROLA INC

Inventor： BLACK GREGORY REDMOND ,  HIETALA ALEXANDER WAYNE ,  BURNS MARK ROBERT

IPC: H04B1/69 ,  H04B15/04 ,  H04B1/10 ,  H04B1/18 ,  H04B1/66 ,  H04B7/005 ,  H04B7/24 ,  H04B7/26 ,  H04B15/00

Abstract: A communication device (104) comprises a receiver circuit (108) receiving a modulated receive signal. A reference oscillator (132) generates a first clock signal at a first frequency, the first clock signal having harmonics. Circuitry (130) coupled to the reference oscillator and to the receiver responds to the first clock signal to produce a signal used by the receiver to reduce the frequency of the modulating signal. A frequency spreading circuit (134) is also coupled to the reference oscillator to modulate the first clock signal with a frequency spreading signal to produce a modulated clock signal including modulated harmonic frequency components. The frequency spreading circuit selectively combines the frequency spreading signal and the first clock signal. A control circuit (114) controls the frequency spreading circuit to modulate first clock signal with the frequency spreading signal when the selected received signal includes a harmonic of the first clock signal.

公开(公告)号：GB2342796A

公开(公告)日：2000-04-19

申请号：GB9924068

申请日：1999-10-12

Applicant: MOTOROLA INC

Inventor： HIETALA ALEXANDER WAYNE ,  ARORA ARVIND S

IPC: H03J7/10 ,  H03J1/00 ,  H03J7/04 ,  H03L7/10

Abstract: Automatic frequency control (AFC) range extension, for use in a communication device, involves varying receive bandwidth of the communication device 100 to facilitate AFC. In this method, the receive bandwidth is set to a first , wide setting for AFC acquisition purposes (figure 2, no.208) A frequency error associated with a received AFC signal is determined (figure2, no. 212) and receive reception is adjusted (figure 2, no. 218) to reduce frequency error in the communication device 100. Once the frequency error is below a predetermined threshold (figure 2, no. 214), the receive bandwidth is set to a second setting different from the first setting for normal reception (figure 2, no. 220). If, during the operation of the apparatus at the second receive setting, the frequency error should exceed a second predetermined threshold (figure 2, no. 226), the receive bandwidth reverts to the first receive setting. The use of AFC range extension means a high frequency communication device can use a low accuracy crystal in its reference oscillator.

公开(公告)号：GB2302770B

公开(公告)日：1999-12-01

申请号：GB9610845

申请日：1996-05-23

Applicant: MOTOROLA INC

Inventor： JANSSEN JOHN J ,  HIETALA ALEXANDER WAYNE

IPC: H04B1/40 ,  G01R31/28 ,  G01R31/36 ,  G01R31/40 ,  H02J7/00 ,  H04B1/38 ,  H04B7/26 ,  H04M19/08 ,  H02H3/24 ,  H02H3/05 ,  H02H7/18 ,  H02H11/00 ,  H04B1/16 ,  H04Q7/32

Abstract: A portable radio communication device (303) includes power control circuitry (315) for monitoring the voltage level incoming from a battery (317), and provides power to the rest of the radio communication device (303). The power control circuitry (315) includes a boost regulator (407) that is used to generate an internal reference signal for use throughout the radio communication device including an analog to digital converter (ADC) for digitizing the battery voltage for use by the power control circuitry (315). The power control circuitry (315) compares the digitized battery voltage to thresholds to control power to the remainder of the radio communication device (303). Additionally, a secondary comparator (413) is provided to prevent damage to the battery and radio communication device circuitry. The secondary comparator uses multiple undervoltage thresholds depending upon the power state of the radio communication device (303).

公开(公告)号：GB2336955A

公开(公告)日：1999-11-03

申请号：GB9918678

申请日：1996-05-23

Applicant: MOTOROLA INC

Inventor： JANSSEN JOHN J ,  HIETALA ALEXANDER WAYNE

IPC: G01R31/36 ,  G01R31/40 ,  H02J7/00 ,  H04M19/08 ,  H02H3/24

Abstract: Power supply to parts of the a portable electronic device, particularly a portable radio telephone, is cut off when the battery voltage falls below a software threshold level. The battery voltage is supplied to a boost regulator 407 which provides an internal reference signal to various circuits, including an analog to digital converter (ADC) 403. ADC 403 uses the reference signal to sample the battery voltage to provide the digitized battery voltage 427 to a processor 405 for comparison therein with the software threshold. Use of boost regulator 407 to provide the internal reference signal allows shutoff at a lower undervoltage value. When the device is in a powered-up state, a hardware shutoff circuit 417 shuts off circuitry if a comparator 413 detects that the battery voltage is below a first hardware undervoltage threshold level which is lower than the software threshold; this provides a backup or failsafe if the software power control circuitry fails. A second hardware undervoltage threshold level, higher than the first, applies when the device is in a powered-off state. When the user operates a power key to power-on the device, the shutoff circuit 417 will prevent power-up if the battery voltage is below this higher second threshold; this prevents the radio communication device from powering-up in an illegal state. The power supply control is of particular use with batteries having a linear fall in voltage during discharge, especially lithium ion batteries, since it allows a larger portion of the energy in the battery to be used before powering-off.

公开(公告)号：DE19707749A1

公开(公告)日：1997-11-06

申请号：DE19707749

申请日：1997-02-26

Applicant: MOTOROLA INC

Inventor： BLACK GREGORY REDMOND ,  HIETALA ALEXANDER WAYNE ,  BURNS MARK ROBERT

IPC: H04B1/66 ,  H04B1/69

Abstract: The radio transceiver includes receives (108) a communication signal on a selected channel. A reference oscillator (132) generates a master clock signal at a given frequency, with harmonics. A frequency synthesiser (130) divides the clock signal to produce a signal for demodulating the received signal. A frequency spreading circuit (134) is coupled to the reference oscillator and to the receiver circuit to modulate the clock signal in order to generate a frequency spread clock signal. The harmonic components of the frequency spread clock signal are spread over a frequency bandwidth greater than the channel bandwidth. A control circuit (114) selectively operates the frequency spreading circuit to modulate the clock signal when a received signal on the selected channel includes a master clock signal harmonic.

公开(公告)号：DE19707749B4

公开(公告)日：2005-12-01

申请号：DE19707749

申请日：1997-02-26

Applicant: MOTOROLA INC

Inventor： BLACK GREGORY REDMOND ,  HIETALA ALEXANDER WAYNE ,  BURNS MARK ROBERT

IPC: H04B1/66 ,  H04B1/69

公开(公告)号：GB2343800B

公开(公告)日：2001-01-10

申请号：GB9925787

申请日：1999-11-01

Applicant: MOTOROLA INC

Inventor： BLACK GREGORY R ,  HIETALA ALEXANDER WAYNE

IPC: H03G3/30 ,  H03G3/20

Abstract: A wireless communication device (202), such as a cellular telephone, has a power amplifier (218) and a power amplifier control (222). The power amplifier (218) is selectively controllable to amplify, to different output power levels, a signal for transmission. In a high power mode requiring amplification of the signal to a high output power level, the power amplifier control (222) controls the power amplifier to amplify the signal according to a predetermined amplitude waveform (106). In a low power mode requiring amplification of the signal to a low output power level, the power amplifier control controls the power amplifier to amplify the signal according to a delayed one of the predetermined amplitude waveform (300).

公开(公告)号：GB2343568A

公开(公告)日：2000-05-10

申请号：GB9926075

申请日：1999-11-03

Applicant: MOTOROLA INC

Inventor： HIETALA ALEXANDER WAYNE ,  GONZALEZ DAVID M

IPC: H03L7/22 ,  H03L7/06 ,  H03L7/089 ,  H03L7/093 ,  H03L7/14 ,  H03L7/18 ,  H04B1/26 ,  H03D13/00

Abstract: A PLL (212) includes a phase detector (202) and a charge pump (210 or 212). The phase detector (300) includes a first D-type flip flop (302), a second D-type flip flop (304) and an AND gate forming a reset circuit (306). The charge pump (210 or 212) includes an up current source (308) and a down current source (310). The up current source (308) provides a constant current. The down current source (310) varies responsive to an output signal (207) generated by the second D-type flip flop (304). The constant current provided by the up current source (308) is made to be less than one half the current provided by the down current source (310) to bias the charge pump (210 or 212) in a negative direction to minimize false locks between the phase of a divided reference frequency signal (206) and the phase of a divided voltage controlled oscillator frequency signal (209). Alternatively, the up current source (308) may be controlled in an analogous manner with the down current source (310) being held constant to achieve a similar effect and advantage.