公开(公告)号：DE69616463T2

公开(公告)日：2002-05-23

申请号：DE69616463

申请日：1996-08-22

Applicant: MOTOROLA INC

Inventor： CIRCELLO JOSEPH C ,  HOHL WILLIAM A

IPC: G06F11/28 ,  G06F11/36 ,  G06F11/00

Abstract: A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.

公开(公告)号：DE69616463D1

公开(公告)日：2001-12-06

申请号：DE69616463

申请日：1996-08-22

Applicant: MOTOROLA INC

Inventor： CIRCELLO JOSEPH C ,  HOHL WILLIAM A

IPC: G06F11/28 ,  G06F11/36 ,  G06F11/00

Abstract: A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.

公开(公告)号：DE69616917T2

公开(公告)日：2002-06-06

申请号：DE69616917

申请日：1996-08-22

Applicant: MOTOROLA INC

Inventor： HOHL WILLIAM A ,  CIRCELLO JOSEPH C

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/36 ,  G06F11/00

Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

公开(公告)号：DE69616917D1

公开(公告)日：2001-12-20

申请号：DE69616917

申请日：1996-08-22

Applicant: MOTOROLA INC

Inventor： HOHL WILLIAM A ,  CIRCELLO JOSEPH C

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/36 ,  G06F11/00

Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).