公开(公告)号：JP2000029700A

公开(公告)日：2000-01-28

申请号：JP17069799

申请日：1999-06-17

Applicant: MOTOROLA INC

Inventor： LEE WAN LEE ,  MOYER WILLIAM C ,  SCOTT JEFFREY W ,  ARENDS JOHN H

IPC: G06F9/38 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To minimize a clock cycle number by composing the system of a stage where a program loop is defined and a stage where a loop value is determined according to a backward branch instruction. SOLUTION: A data processor 10 is equipped with a CPU 12, a memory 14, a bus interface module 16, and other modules 18 coupled with one another in two directions through a bus 20. The memory 14 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 24. The CPU12 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 22. The data processor 10 executes instructions collected in order from the memory 14 until it encounters a variation instruction for a flow such as a branch instruction. In this case, the backward branch instruction executes branching to a target address in the memory 14, defines a program loop, and sets a loop value according to the backward branch instruction.

公开(公告)号：JPH10232830A

公开(公告)日：1998-09-02

申请号：JP32522897

申请日：1997-11-11

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  LEE WAN LEE ,  JOHN ARENS

IPC: G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To suppress the size of entire integrated circuit minimum without considerably reducing a cache size by managing the entry invalidization of loop cache by detecting the comparison logic and flow change state of global tag and individual tag. SOLUTION: A loop cache 26 applies three control bits to a state machine. A cache hit logic 64 is connected to a comparator 60, comparator 62 and effective bit array 54. When a global tag(GTAG) section 46 of instruction address 40 is coincident with a stored GTAG value 48, an individual tag(ITAG) section 44 of instruction address 40 is coincident with the entry of ITAG part selected by a loop cache(LCACHE) index 42 and the effective bit in the effective bit array 54 selected by the LCACHE index 42 is asserted, the cache hit logic 64 shows cache hit.