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公开(公告)号：AU676436B2
公开(公告)日：1997-03-06
申请号：AU2272395
申请日：1995-03-27
Applicant: MOTOROLA INC
Inventor： AUYEUNG CHEUNG , O'CONNELL KEVIN JOSEPH , LEVINE STEPHEN NORMAN
Abstract: Whether to encode a present video block of an incoming video frame, i.e. intra code, or whether to encode the difference between the present video block of the incoming frame and a best match video block from a previously stored video frame, i.e. non-intra code, is determined in a video compression system 100. First the present video block is divided into a predetermined number of sub blocks 301. Then an average pixel value is calculated for each sub block 302 and used along with the individual pixel values of the sub block to determine sub block deviations 303. The sub block deviations are used to compute a present video block deviation 303. The present video block deviation is then compared with an error deviation 306 that is calculated based upon the present video block pixel values and the best match video block pixel values 305. If the comparison is favorable, then the difference between the present video block and the best match video block are encoded. If the comparison is unfavorable, then the present video block is encoded.
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公开(公告)号：AU4520096A
公开(公告)日：1996-09-11
申请号：AU4520096
申请日：1995-12-14
Applicant: MOTOROLA INC
Inventor： AUYEUNG CHEUNG , LINDSLEY BRETT LOUIS , LEVINE STEPHEN NORMAN
Abstract: The present invention is method and apparatus for preventing overflow and underflow of an encoder buffer in a video compression system. A virtual buffer is created in a rate controller to model the decoder buffer fullness (102). A sequence of bits is generated by an encoder (104). The encoder is controlled by the rate controller to prevent a decoder buffer underflow and overflow. Then, the sequence of bits is received by the encoder buffer to produce a bitstream (106). The bitstream corresponds to an instantaneous channel bitrate. The bitstream is transmitted from the encoder buffer to a decoder buffer following a delay (108). The delay is controlled by a rate controller to synchronize an encoder buffer fullness with a virtual buffer fullness (110). The synchronization prevents overflow and underflow of the encoder buffer.
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3.发明专利
公开(公告)号：CA2185704A1
公开(公告)日：1996-08-29
申请号：CA2185704
申请日：1995-12-14
Applicant: MOTOROLA INC
Inventor： AUYEUNG CHEUNG , LEVINE STEPHEN NORMAN , KOSMACH JAMES JOSEPH
IPC: G06T9/00 , H04N7/32 , H04N7/50 , H04N21/234 , H04N21/44
Abstract: The present invention is method, rate controller, and system for preventing overflow and underflow of a decoder buffer in a video compression system. First, a plurality of quantized video bits is received from an encoder (102). The plurality of quantized video bits correspond to a video frame type. Then, a virtual buffer is created, in a rate controller, to model fullness of a decoder buffer, based on the quantized video bits, to produce a virtual buffer fullness (104). A quantization stepsize estimate is finally determined, in a rate controller, based on at least a first predetermined target bit allocation, the video frame type, and the virtual buffer fullness (106). The quantization step size estimate will prevent the overflow and underflow of a decoder buffer.
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公开(公告)号：DK0479950T3
公开(公告)日：1997-09-22
申请号：DK90917881
申请日：1990-06-22
Applicant: MOTOROLA INC
IPC: H04B7/005 , H04B7/26 , H04J3/00 , H04J3/16 , H04L7/00 , H04M11/00 , H04W56/00 , H04Q7/00 , H04Q9/00
Abstract: In a Time Division Multiple Access (TDMA) cellular system, there is provided a mechanism for synchronization and equalization comprising: providing synchronization information (S/S) sufficiently removed from the start of a TDM slot so as to maintain the integrity of that synchronization information (S/S) at adjacent cells and providing that synchronization information (S/S) not so far removed from the start of the slot as to necessitate adaptive equalization of information preceding the synchronization information (S/S) for sufficiently reliable recovery. The equalization is further enhanced by providing, roughly midway between the synchronization information (S/S) and the end of the slot, additional information (CC) upon which equalization may retrain. Accordingly, equalizers perform retrospective, non-adaptive equalization of information preceding the synchronization information (S/S), perform adaptive equalization of information following that synchronization information (S/S), and retrain utilizing known bit-sequences elsewhere within the TDM slot; the additional information (CC) comprises known bit-sequences identifying cells.
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公开(公告)号：AU678926B2
公开(公告)日：1997-06-12
申请号：AU4520096
申请日：1995-12-14
Applicant: MOTOROLA INC
Inventor： AUYEUNG CHEUNG , LINDSLEY BRETT LOUIS , LEVINE STEPHEN NORMAN
Abstract: The present invention is method and apparatus for preventing overflow and underflow of an encoder buffer in a video compression system. A virtual buffer is created in a rate controller to model the decoder buffer fullness (102). A sequence of bits is generated by an encoder (104). The encoder is controlled by the rate controller to prevent a decoder buffer underflow and overflow. Then, the sequence of bits is received by the encoder buffer to produce a bitstream (106). The bitstream corresponds to an instantaneous channel bitrate. The bitstream is transmitted from the encoder buffer to a decoder buffer following a delay (108). The delay is controlled by a rate controller to synchronize an encoder buffer fullness with a virtual buffer fullness (110). The synchronization prevents overflow and underflow of the encoder buffer.
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Patent Agency Ranking
公开(公告)号：ES2098277T3
公开(公告)日：1997-05-01
申请号：ES90917881
申请日：1990-06-22
Applicant: MOTOROLA INC
IPC: H04B7/005 , H04B7/26 , H04J3/00 , H04J3/16 , H04L7/00 , H04M11/00 , H04W56/00 , H04Q7/00 , H04Q9/00 , H04B7/212
Abstract: In a Time Division Multiple Access (TDMA) cellular system, there is provided a mechanism for synchronization and equalization comprising: providing synchronization information (S/S) sufficiently removed from the start of a TDM slot so as to maintain the integrity of that synchronization information (S/S) at adjacent cells and providing that synchronization information (S/S) not so far removed from the start of the slot as to necessitate adaptive equalization of information preceding the synchronization information (S/S) for sufficiently reliable recovery. The equalization is further enhanced by providing, roughly midway between the synchronization information (S/S) and the end of the slot, additional information (CC) upon which equalization may retrain. Accordingly, equalizers perform retrospective, non-adaptive equalization of information preceding the synchronization information (S/S), perform adaptive equalization of information following that synchronization information (S/S), and retrain utilizing known bit-sequences elsewhere within the TDM slot; the additional information (CC) comprises known bit-sequences identifying cells.
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公开(公告)号：CA2178943A1
公开(公告)日：1996-05-30
申请号：CA2178943
申请日：1995-09-05
Applicant: MOTOROLA INC
Inventor： AUYEUNG CHEUNG , LEVINE STEPHEN NORMAN , KOSMACH JAMES JOSEPH
Abstract: The present invention provides a method (100) and device (200) for allocating bits to video pictures in a video compression system. A sequence of video frames or pictures is received, and the number of bits used to compress a previously encoded frame and a signal-to-noise ratio for the immediately previously encoded video frame are determined. Rate distortion model parameters are updated. Then, first, second, and third deviations are determined. Finally, the bit allocation for the frame is determined based on the first number of bits used to compress a previously encoded frame, the first deviation, the second deviation, and the third deviation.
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公开(公告)号：BR9007691A
公开(公告)日：1992-07-07
申请号：BR9007691
申请日：1990-09-04
Applicant: MOTOROLA INC
Inventor： LEVINE STEPHEN NORMAN , IRVINE ROBERT JOHNSON
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公开(公告)号：AU5952290A
公开(公告)日：1991-01-17
申请号：AU5952290
申请日：1990-06-22
Applicant: MOTOROLA INC
IPC: H04B7/005 , H04B7/26 , H04J3/00 , H04J3/16 , H04L7/00 , H04M11/00 , H04W56/00 , H04Q7/00 , H04Q9/00
Abstract: In a Time Division Multiple Access (TDMA) cellular system, there is provided a mechanism for synchronization and equalization comprising: providing synchronization information (S/S) sufficiently removed from the start of a TDM slot so as to maintain the integrity of that synchronization information (S/S) at adjacent cells and providing that synchronization information (S/S) not so far removed from the start of the slot as to necessitate adaptive equalization of information preceding the synchronization information (S/S) for sufficiently reliable recovery. The equalization is further enhanced by providing, roughly midway between the synchronization information (S/S) and the end of the slot, additional information (CC) upon which equalization may retrain. Accordingly, equalizers perform retrospective, non-adaptive equalization of information preceding the synchronization information (S/S), perform adaptive equalization of information following that synchronization information (S/S), and retrain utilizing known bit-sequences elsewhere within the TDM slot; the additional information (CC) comprises known bit-sequences identifying cells.
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公开(公告)号：AU6147886A
公开(公告)日：1987-03-24
申请号：AU6147886
申请日：1986-07-11
Applicant: MOTOROLA INC
Inventor： LEVINE STEPHEN NORMAN , LEITICH ALBERT J
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