公开(公告)号：DE69033160D1

公开(公告)日：1999-07-22

申请号：DE69033160

申请日：1990-03-15

Applicant: MOTOROLA INC

Inventor： LUNN GERALD W ,  TONG HING YIP

IPC: H04N5/265 ,  H04N5/445 ,  H04N5/46 ,  H04N9/64 ,  H04N7/01

Abstract: A television receiver including a MPU (15) with OSD cicuitry (20) on a single chip. The OSD circuitry includes multisystem detection circuitry (22) which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL (21) to synchronize the receiver to the received standard. The PLL includes a VCO (35) having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector (39), which alternating phases cause jitter in the display.

公开(公告)号：DE69033160T2

公开(公告)日：2000-01-27

申请号：DE69033160

申请日：1990-03-15

Applicant: MOTOROLA INC

Inventor： LUNN GERALD W ,  TONG HING YIP

IPC: H04N5/265 ,  H04N5/445 ,  H04N5/46 ,  H04N9/64 ,  H04N7/01

Abstract: A television receiver including a MPU (15) with OSD cicuitry (20) on a single chip. The OSD circuitry includes multisystem detection circuitry (22) which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL (21) to synchronize the receiver to the received standard. The PLL includes a VCO (35) having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector (39), which alternating phases cause jitter in the display.