2.
    发明专利
    未知

    公开(公告)号:DE69033156T2

    公开(公告)日:2000-01-27

    申请号:DE69033156

    申请日:1990-03-23

    Applicant: MOTOROLA INC

    Abstract: A TV receiver including a microprocessor (15) and on screen display circuitry (20) on a single semiconductor chip. The OSD includes half dot logic and shifting circuitry (32, 34) to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enchancing circuit (75) to generate a black surround. A simplified window generator (36) is combined therewith to further improve the characters.

    3.
    发明专利
    未知

    公开(公告)号:DE69033160D1

    公开(公告)日:1999-07-22

    申请号:DE69033160

    申请日:1990-03-15

    Applicant: MOTOROLA INC

    Abstract: A television receiver including a MPU (15) with OSD cicuitry (20) on a single chip. The OSD circuitry includes multisystem detection circuitry (22) which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL (21) to synchronize the receiver to the received standard. The PLL includes a VCO (35) having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector (39), which alternating phases cause jitter in the display.

    4.
    发明专利
    未知

    公开(公告)号:DE69034097T2

    公开(公告)日:2004-04-01

    申请号:DE69034097

    申请日:1990-03-23

    Applicant: MOTOROLA INC

    Abstract: A TV receiver including a microprocessor (15) and on screen display circuitry (20) on a single semiconductor chip. The OSD includes half dot logic and shifting circuitry (32, 34) to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enchancing circuit (75) to generate a black surround. A simplified window generator (36) is combined therewith to further improve the characters.

    5.
    发明专利
    未知

    公开(公告)号:DE69034097D1

    公开(公告)日:2003-10-02

    申请号:DE69034097

    申请日:1990-03-23

    Applicant: MOTOROLA INC

    Abstract: A TV receiver including a microprocessor (15) and on screen display circuitry (20) on a single semiconductor chip. The OSD includes half dot logic and shifting circuitry (32, 34) to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enchancing circuit (75) to generate a black surround. A simplified window generator (36) is combined therewith to further improve the characters.

    6.
    发明专利
    未知

    公开(公告)号:DE69033156D1

    公开(公告)日:1999-07-15

    申请号:DE69033156

    申请日:1990-03-23

    Applicant: MOTOROLA INC

    Abstract: A TV receiver including a microprocessor (15) and on screen display circuitry (20) on a single semiconductor chip. The OSD includes half dot logic and shifting circuitry (32, 34) to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enchancing circuit (75) to generate a black surround. A simplified window generator (36) is combined therewith to further improve the characters.

    7.
    发明专利
    未知

    公开(公告)号:DE69033160T2

    公开(公告)日:2000-01-27

    申请号:DE69033160

    申请日:1990-03-15

    Applicant: MOTOROLA INC

    Abstract: A television receiver including a MPU (15) with OSD cicuitry (20) on a single chip. The OSD circuitry includes multisystem detection circuitry (22) which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL (21) to synchronize the receiver to the received standard. The PLL includes a VCO (35) having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector (39), which alternating phases cause jitter in the display.

    Tv receiver including multistandard osd

    公开(公告)号:SG67898A1

    公开(公告)日:1999-10-19

    申请号:SG1996004695

    申请日:1990-03-15

    Applicant: MOTOROLA INC

    Abstract: A television receiver including a MPU (15) with OSD cicuitry (20) on a single chip. The OSD circuitry includes multisystem detection circuitry (22) which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL (21) to synchronize the receiver to the received standard. The PLL includes a VCO (35) having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector (39), which alternating phases cause jitter in the display.

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