公开(公告)号：JP2000030460A

公开(公告)日：2000-01-28

申请号：JP17069699

申请日：1999-06-17

Applicant: MOTOROLA INC

Inventor： ALAN S ROSS ,  NOGLE SCOTT GEORGE

IPC: G11C11/41 ,  G11C7/00

Abstract: PROBLEM TO BE SOLVED: To obtain a dual port RAM which is inexpensive and whose speed is high and whose capacity is large by providing an arbitration circuit judging which of first and second addresses is given to plural memories during the access to an integrated circuit memory to utilize single port RAMs. SOLUTION: A memory 20 includes a single port SRAM array 21, an arbitration circuit 24, bonding pads 26, 28, an input part 30 and an output part 50. At the time of an operation, the memory 20 functions as the static random access memory(SRAM) of a full dual port. The memory 20 generates an access request to the array 21 responding to an external access request. The arbitration circuit 24 assures that the earlier access request between two access requests is given to the array 21 except a time when the two access requests are actually received simultaneously and the priority is given to an X port when the requests are received simultaneously.

公开(公告)号：JPH11232877A

公开(公告)日：1999-08-27

申请号：JP22108498

申请日：1998-07-21

Applicant: MOTOROLA INC

Inventor： NOGLE SCOTT GEORGE ,  ROTH ALAN S ,  HO SHUANG LI

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To realize a dual port RAM which uses a single port SRAM cell, can be manufactured by using a small integrated circuit surface area, is inexpensive and large, and operates at high speed. SOLUTION: A pipelined dual port integrated circuit memory 20 comprises an array 30 of static random access memory (SRAM) cells, and each of memory cells 80 is connected to a single word line 72 and a pair of single bit lines 74, 76. A control circuit 32 controls access to a memory cell substantially simultaneous request to access is successively served in a clock signal of a single cycle of a data processor accessing to the memory 20. An address collision detector compares addresses given to two ports, and generates a matching signal used for deciding which port is served first out of two ports independently whichever port out or written in.

公开(公告)号：DE69126255T2

公开(公告)日：1997-11-13

申请号：DE69126255

申请日：1991-07-08

Applicant: MOTOROLA INC

Inventor： NOGLE SCOTT GEORGE

IPC: G11C11/41 ,  G11C7/12 ,  G11C11/417 ,  G11C11/419 ,  G11C7/00

Abstract: A BICMOS bit line load (74) for a memory (30) with improved-speed write recovery and improved reliability. The bit line load (74) comprises first (103) and second (104) bipolar transistors coupled to first (72) and second (73) bit lines of a differential bit line pair (72, 73). The improvement in speed is accomplished through the use of the bipolar transistors (103, 104) which generally switch faster than corresponding MOS transistors. For bipolar transistors, however, mean lifetime under worst case conditions is related to reverse bias voltage by an inverse semilogarithmic relationship. The improvement in reliability occurs by limiting a reverse bias voltage to which base-emitter junctions of the bipolar transistors (103, 104) are subjected to increase the mean failure time beyond a predetermined life, for example 10 years, under worst case conditions.

公开(公告)号：DE69124160D1

公开(公告)日：1997-02-27

申请号：DE69124160

申请日：1991-07-29

Applicant: MOTOROLA INC

Inventor： NOGLE SCOTT GEORGE

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/414 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/094

Abstract: A BICMOS logic circuit (160) with self-boosting immunity comprises a resistor (162), first (161) and second (168) transistors, a switching portion (163, 164), and a discharge portion (165, 166, 167, 169). The resistor (162) and first transistor (161) bias the switching portion (163, 164) to first and second reference voltages, which may be equal. The second transistor (168) is a bipolar transistor providing an output signal to a load. The switching portion (163, 164) couples the bias voltage provided by the resistor (162) and the first transistor (161 ) to the base of the second transistor (168) in response to a true result of a logic operation on at least one input signal, and couples the base of the second transistor (168) to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion (165, 166, 167, 169) couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation.

公开(公告)号：DE69124160T2

公开(公告)日：1997-07-10

申请号：DE69124160

申请日：1991-07-29

Applicant: MOTOROLA INC

Inventor： NOGLE SCOTT GEORGE

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/414 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/094

Abstract: A BICMOS logic circuit (160) with self-boosting immunity comprises a resistor (162), first (161) and second (168) transistors, a switching portion (163, 164), and a discharge portion (165, 166, 167, 169). The resistor (162) and first transistor (161) bias the switching portion (163, 164) to first and second reference voltages, which may be equal. The second transistor (168) is a bipolar transistor providing an output signal to a load. The switching portion (163, 164) couples the bias voltage provided by the resistor (162) and the first transistor (161 ) to the base of the second transistor (168) in response to a true result of a logic operation on at least one input signal, and couples the base of the second transistor (168) to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion (165, 166, 167, 169) couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation.

公开(公告)号：DE69126255D1

公开(公告)日：1997-07-03

申请号：DE69126255

申请日：1991-07-08

Applicant: MOTOROLA INC

Inventor： NOGLE SCOTT GEORGE

IPC: G11C11/41 ,  G11C7/12 ,  G11C11/417 ,  G11C11/419 ,  G11C7/00

Abstract: A BICMOS bit line load (74) for a memory (30) with improved-speed write recovery and improved reliability. The bit line load (74) comprises first (103) and second (104) bipolar transistors coupled to first (72) and second (73) bit lines of a differential bit line pair (72, 73). The improvement in speed is accomplished through the use of the bipolar transistors (103, 104) which generally switch faster than corresponding MOS transistors. For bipolar transistors, however, mean lifetime under worst case conditions is related to reverse bias voltage by an inverse semilogarithmic relationship. The improvement in reliability occurs by limiting a reverse bias voltage to which base-emitter junctions of the bipolar transistors (103, 104) are subjected to increase the mean failure time beyond a predetermined life, for example 10 years, under worst case conditions.