公开(公告)号：BR8106699A

公开(公告)日：1981-12-22

申请号：BR8106699

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： OOMS W

IPC: H03L7/18 ,  H03K23/66 ,  H03L7/193 ,  H03L7/197 ,  H03K21/36

Abstract: An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler of limited size is used in conjunction with a second prescaler to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing costs and power consumption.

公开(公告)号：BR8106697A

公开(公告)日：1981-12-22

申请号：BR8106697

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： OOMS W ,  BARNETT R

IPC: H03L7/18 ,  H03K23/66 ,  H03K21/36

公开(公告)号：WO1981002371A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000010

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  OOMS W

IPC: H03K21/36

CPC classification number: H03L7/193 ,  H03K23/667

Abstract: An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler (132) of limited size is used in conjunction with a second prescaler (170) to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing cost and power consumption.

公开(公告)号：WO1981002372A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000011

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  BARNETT R ,  OOMS W

IPC: H03K21/36

CPC classification number: H03K23/667

Abstract: A high frequency divider suitable for use in a frequency synthesizer using a dual modulus prescaler (10) and two counters (30, 40) to achieve high speed and low current drain. The input signal is alternately divided by one of the two moduli in the prescaler and then alternately divided by one of the two counters. Each of the two counters is reset while the other is counting thereby reducing circuit complexity and increasing circuit speed.