公开(公告)号：BR8106834A

公开(公告)日：1981-12-22

申请号：BR8106834

申请日：1981-01-09

Applicant: MOTOROLA INC

Inventor： SWISHER S ,  GRINER P ,  BARNETT R

IPC: H03L7/18 ,  H03L7/10 ,  H03L7/107 ,  H03L7/187

Abstract: An improved frequency synthesizer utilizes a first order loop and sample-and-hold phase detector with optimized gain to obtain very fast frequency locking characteristics. In addition, synchronization of the programming of the loop divider and of the range shifting the voltage controlled oscillator is also utilized. An adaptive loop filter is provided to allow a first order loop to be used for lock acquisition and still maintain excellent noise performance after lock has been obtained.

公开(公告)号：BR8106697A

公开(公告)日：1981-12-22

申请号：BR8106697

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： OOMS W ,  BARNETT R

IPC: H03L7/18 ,  H03K23/66 ,  H03K21/36

公开(公告)号：WO1981002497A1

公开(公告)日：1981-09-03

申请号：PCT/US1981000046

申请日：1981-01-09

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SWISHER S ,  BARNETT R ,  GRINER P

IPC: H03L07/18

CPC classification number: H03L7/187 ,  H03L7/107 ,  H03L2207/06

Abstract: An improved frequency synthesizer utilizes a first order loop and sample-and-hold phase detector (20) with optimized gain to obtain very fast frequency locking characteristics. In addition, synchronization of the programming of the loop divider (34) and of the range shifting the voltage controlled oscillator (30) is also utilized. An adaptive loop filter (100) is provided to allow a first order loop to be used for lock acquisition and still maintain excellent noise performance after lock has been obtained.

公开(公告)号：WO1981002372A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000011

申请日：1981-01-05

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  BARNETT R ,  OOMS W

IPC: H03K21/36

CPC classification number: H03K23/667

Abstract: A high frequency divider suitable for use in a frequency synthesizer using a dual modulus prescaler (10) and two counters (30, 40) to achieve high speed and low current drain. The input signal is alternately divided by one of the two moduli in the prescaler and then alternately divided by one of the two counters. Each of the two counters is reset while the other is counting thereby reducing circuit complexity and increasing circuit speed.