METHOD FOR PRINTED CIRCUIT BOARD PANELIZATION
    4.
    发明申请
    METHOD FOR PRINTED CIRCUIT BOARD PANELIZATION 审中-公开
    印刷电路板组合方法

    公开(公告)号:WO2005041624A3

    公开(公告)日:2007-08-09

    申请号:PCT/US2004031794

    申请日:2004-09-28

    CPC classification number: G06F17/50 H05K3/0005 H05K3/0052

    Abstract: A method for panel optimization provides for optimal layout of printed circuit boards (302-306) on factory arrays (104), as well as the layout of arrays on panels (102). By using nesting algorithms to quickly simulate a large number of permutations, an optimal panelization solution can be quickly reached. The method includes the steps of collecting the necessary data (402), performing a panel dimension loop, an array length loop, and an array width loop. For every case, a total efficiency factor is calculated (422) to help determine the optimal layout.

    Abstract translation: 用于面板优化的方法提供工厂阵列(104)上的印刷电路板(302-306)的最佳布局以及面板(102)上的阵列的布局。 通过使用嵌套算法快速模拟大量的排列,可以快速达到最佳的镶板化解决方案。 该方法包括收集所需数据(402),执行面板尺寸环,阵列长度循环和阵列宽度循环的步骤。 对于每种情况,计算总效率因子(422)以帮助确定最佳布局。

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