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    Master slave flip-flop
    2.
    发明授权
    Master slave flip-flop 失效
    主从SLIPVE FLIP-FLOP

    公开(公告)号：US3617776A

    公开(公告)日：1971-11-02

    申请号：US3617776D

    申请日：1969-03-13

    Applicant: MOTOROLA INC

    Inventor： PRIEL URY

    IPC: H03K3/289 ,  H03K19/086 ,  H03K3/12

    CPC classification number: H03K3/289 ,  H03K19/0866

    Abstract: Disclosed is a master slave flip-flop including two bistable logic stages, each of which includes transistors which are crossconnected to alternately conduct as binary information is applied to the stages. Both logic stages are connected to receive clock signals which enable binary information to be applied to and stored by one of the two logic stages and thereafter shifted into the other stage when the level of clock signals changes.

    Clocked delay type flip flop
    6.
    发明专利
    Clocked delay type flip flop 未知

    公开(公告)号：GB1139628A

    公开(公告)日：1969-01-08

    申请号：GB5182967

    申请日：1967-11-14

    Applicant: MOTOROLA INC

    Inventor： SEELBACH WALTER CHRISTIAN ,  PRIEL URY

    IPC: H03K3/037 ,  H03K3/289

    Abstract: 1,139,628. Transistor bistable circuits. MOTOROLA, Inc. 14 Nov., 1967 [16 Dec., 1966], No. 51829/67. Heading H3T. A bistable circuit comprises a master bistable circuit 9 with its outputs 35, 37 connected to a slave bistable circuit 7 and a clock circuit 6 which locks the master and enables the slave when applied clock signals are at one logical level, and which locks the slave and enables the master when the clock signals are at another logical level. Assume initially that the clock pulse C is at a low level, then transistor 82 is overidden by transistor 80 to enable transistor 74. With a low level input at AN, transistor 70 overides transistor 74 switching off transistor 56 to give a low level output at QM and switching on transister 58 to give a high level output at #QM. When clock C goes to its high level, transistor 88 switches on switching on transistor 82 to lock the master, and switching on transistor 34 to enable the slave. The high QM and low #QM inputs now set the slave to Q high and Q low. Reversion of clock C to its low level locks the slave in this state and enables the master to respond again to the A, R, or S inputs. A high A switches the master to QM high and #QM low. An input at S or R will set or reset both master and slave irrespective of the clock level. For example a high reset R will switch on transistor 28 slightly before transistor 34 thus resetting the slave. The various transistors are biased from a circuit 8 which includes temperature stabilizing diodes 96, 98.

    Clocked r-s flip-flop
    7.
    发明专利
    Clocked r-s flip-flop 未知

    公开(公告)号：GB1119956A

    公开(公告)日：1968-07-17

    申请号：GB3027867

    申请日：1967-06-30

    Applicant: MOTOROLA INC

    Inventor： PRIEL URY ,  SEELBACH WALTER CHRISTIAN

    IPC: H03K3/037

    Abstract: 1,119,956. Transistor logic and bi-stable circuits. MOTOROLA Inc. 30 June, 1967 [13 Sept., 1966], No. 30278/67. Heading H3T. A clocked SET-RESET bi-stable circuit comprises a pair of holding transistors 23, 24 cross-coupled via level shifting transistors 20, 21, the holding transistors 23, 24 being respectively coupled with the parallel combination of further holding transistors 27, 31, SET transistor 32 and RESET transistor 29; transistors 23, 24 being differentially connected to a reference transistor 36, a clocking transistor 38 being differentially connected to the reference transistor 36 and further connected to the holding transistors 27, 31 so as to provide a current path for the circuit when the clock signal overrides a reference voltage applied to the transistor 36. Preferably, in an integrated circuit, transistors 36, 38 have a constant current load formed by transistor 35. The clock signals C may be fed to the clocking transistor 38 via an emitter follower 46. Output emitter followers 44, 45 may be provided. The base potentials of transistors 23, 24 may be stabilized by transistors 40, 41. The current to the conductive transistors normally passes via the reference transistor 36 except when a clock signal is present at C when transistor 48 becomes conductive and enables the state of the circuit to be SET or RESET depending on the presence of signals at R or S.

    10.
    发明专利
    未知

    公开(公告)号：DE1537251A1

    公开(公告)日：1970-05-27

    申请号：DE1537251

    申请日：1967-12-15

    Applicant: MOTOROLA INC

    Inventor： CHRISTIAN SEELBACH WALTER ,  PRIEL URY

    IPC: H03K3/037 ,  H03K3/289 ,  H03K3/286

    Abstract: 1,139,628. Transistor bistable circuits. MOTOROLA, Inc. 14 Nov., 1967 [16 Dec., 1966], No. 51829/67. Heading H3T. A bistable circuit comprises a master bistable circuit 9 with its outputs 35, 37 connected to a slave bistable circuit 7 and a clock circuit 6 which locks the master and enables the slave when applied clock signals are at one logical level, and which locks the slave and enables the master when the clock signals are at another logical level. Assume initially that the clock pulse C is at a low level, then transistor 82 is overidden by transistor 80 to enable transistor 74. With a low level input at AN, transistor 70 overides transistor 74 switching off transistor 56 to give a low level output at QM and switching on transister 58 to give a high level output at #QM. When clock C goes to its high level, transistor 88 switches on switching on transistor 82 to lock the master, and switching on transistor 34 to enable the slave. The high QM and low #QM inputs now set the slave to Q high and Q low. Reversion of clock C to its low level locks the slave in this state and enables the master to respond again to the A, R, or S inputs. A high A switches the master to QM high and #QM low. An input at S or R will set or reset both master and slave irrespective of the clock level. For example a high reset R will switch on transistor 28 slightly before transistor 34 thus resetting the slave. The various transistors are biased from a circuit 8 which includes temperature stabilizing diodes 96, 98.

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