CMOS MICROPROCESSOR ARCHITECTURE
    4.
    发明申请
    CMOS MICROPROCESSOR ARCHITECTURE 审中-公开
    CMOS微处理器架构

    公开(公告)号:WO1981000473A1

    公开(公告)日:1981-02-19

    申请号:PCT/US1980001006

    申请日:1980-08-07

    Applicant: MOTOROLA INC

    CPC classification number: G06F9/321 G06F15/7832

    Abstract: A CMOS microprocessor having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static register. In most cases the registers are connected to two buses. A 5 bit temporary register (34) and an 8 bit program counter (23) are each connected to three buses. An incrementer (21), (38) can provide an increment or decrement function but cannot be used to store functions. A bit code generator (44) is connected to a data bus (12) thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter (33) is capable of directly transferring its contents to the 5 bit temporary register (34). An 8 bit low order incrementer (21) is capable of incrementing three different registers which are an address storage register (22), a program counter (23), and a stack pointer (24). A 5 bit high order incrementer (38) is also capable of incrementing three registers which are an address storage register (32), a program counter (33), and a temporary register (34). An ALU (11) has a first and a second input, which, because of the bus structure used, can both receive data simultaneously.

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