公开(公告)号：HK1004583A1

公开(公告)日：1998-11-27

申请号：HK98102858

申请日：1998-04-04

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY WAYNE ,  TAHERNIA OMID ,  DAVIS WALTER LEE ,  RIVAS MARIO ALBERTO

IPC: H03J5/02 ,  H03L7/18 ,  H03J

Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

公开(公告)号：IN177272B

公开(公告)日：1996-12-21

申请号：IN418DE1990

申请日：1990-05-03

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY WAYNE ,  TAHERNIA OMID ,  DAVIS WALTER LEE ,  RIVAS MARIO ALBERTO

IPC: G06F7/00 ,  G06F15/00

公开(公告)号：AT141452T

公开(公告)日：1996-08-15

申请号：AT90917819

申请日：1990-05-18

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY WAYNE ,  TAHERNIA OMID ,  DAVIS WALTER LEE ,  RIVAS MARIO ALBERTO

IPC: H03L7/18 ,  H03J5/02 ,  H03J1/00

Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.