Method for delineating semiconductor junctions
    2.
    发明授权
    Method for delineating semiconductor junctions 失效
    分解半导体结的方法

    公开(公告)号:US3830665A

    公开(公告)日:1974-08-20

    申请号:US31301072

    申请日:1972-12-07

    Applicant: MOTOROLA INC

    Inventor: ROMAN W WILSON L

    CPC classification number: H01L21/30604 H01L21/00 Y10S148/051 Y10S148/085

    Abstract: A method for etching a groove along a junction between regions of semiconductor material having different dopant concentrations to delineate or isolate the regions forming the junction. Standard concentrations of sirtl etch are used in conjunction with infrared radiation. Wafers in a holder are placed in a container of sirtl etch and exposed to infrared radiation. Preferential etching creates a groove at the semiconductor junction.

    Abstract translation: 沿着具有不同掺杂剂浓度的半导体材料的区域之间的接合处蚀刻凹槽以描绘或隔离形成结的区域的方法。 sirtl蚀刻的标准浓度与红外辐射结合使用。 将保持器中的晶片放置在Sirtl蚀刻的容器中并暴露于红外辐射。 优先蚀刻在半导体结处形成凹槽。

Patent Agency Ranking