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    Semiconductor strain gage and method of fabricating same
    1.
    发明授权
    Semiconductor strain gage and method of fabricating same 失效
    半导体应变片及其制造方法

    公开(公告)号：US3798754A

    公开(公告)日：1974-03-26

    申请号：US25308172

    申请日：1972-05-15

    Applicant: MOTOROLA INC

    Inventor： PRICE J ,  LESK I

    IPC: H01L21/205 ,  G01L1/18 ,  H01L21/00 ,  H01L21/306 ,  H01L29/00 ,  H01L29/84 ,  B01J17/00

    CPC classification number: H01L29/84 ,  G01L1/18 ,  H01L21/00 ,  H01L21/30608 ,  H01L29/00 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S438/928 ,  Y10T29/42 ,  Y10T29/49103

    Abstract: A piezoresistive semiconductor strain gage for transforming mechanical stress into a changed resistance of the semiconductor and therefore a changed electrical current therethrough representative of the amount of stress is described. Also described is a method of fabricating the strain gage that is reliable and results in each produced strain gage having the characteristics of all of the others. The strain gage is comprised of a piezoresistive silicon body having enlarged ends. A KOH etch is made in each end and an epitaxial layer is therein. THEREIN. The epitaxial layer is of the same conductivity type as the piezoresistive silicon but is much more heavily doped to provide low resistance paths to solderable contacts connected to the epitaxially grown material. The combination of enlarged ends and reduced center provides stress amplification, resulting in a greater sensitivity of the strain gage.

    Abstract translation: 描述了用于将机械应力转换为半导体的改变的电阻并因此代表应力量的变化的电流的压阻半导体应变计。 还描述了制造可靠的应变计的方法，并且导致每个生产的具有所有其它特征的应变计。 应变计包括具有扩大端部的压阻硅体。 在每个端部制造KOH蚀刻，其中存在外延层。 好的 该外延层具有与压阻硅相同的导电类型，但是更加重掺杂以提供连接到外延生长材料的可焊接触点的低电阻路径。 扩大端和减少中心的组合提供了应力放大，导致应变计具有更大的灵敏度。

    Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
    3.
    发明授权
    Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor 失效
    用于制造电介质隔离场效应晶体管的控制异相蚀刻工艺

    公开(公告)号：US3755012A

    公开(公告)日：1973-08-28

    申请号：US3755012D

    申请日：1971-03-19

    Applicant: MOTOROLA INC

    Inventor： GEORGE W ,  PRICE J

    IPC: H01L21/762 ,  H01L29/808 ,  H01L7/50 ,  H01L7/00 ,  H01L11/14

    CPC classification number: H01L21/76297 ,  H01L29/808 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/145

    Abstract: There is disclosed an improved junction field effect transistor with dielectric isolation as opposed to isolation by PN junction techniques. The use of the dielectric isolation lowers parasitic capacitance and permits the use of a single gate for the control of the current from the source to the drain of the device. The use of a single gate and the dielectric isolation prevents this parasitic capacitance and the concomitant reduction of the frequency response of the device by eliminating the need for a large area second gate which generates the unwanted parasitic capacitance. In the two gate embodiment of the subject invention, the second gate area is minimized so as to minimize the parasitic capacitance. The gain of the subject device is increased by internally connecting the two gates with a deep diffused region therebetween. There is further disclosed a method for making junction field effect transistors such that the channel width is accurately controlled.

    Abstract translation: 公开了具有介电隔离的改进的结型场效应晶体管，而不是通过PN结技术的隔离。 使用介质隔离降低寄生电容，并允许使用单个栅极来控制从器件的源极到漏极的电流。 单个栅极和介质隔离的使用通过消除对产生不需要的寄生电容的大面积第二栅极的需要来防止该寄生电容和伴随的器件的频率响应的降低。 在本发明的两个栅极实施例中，第二栅极区域被最小化以使寄生电容最小化。 通过内部连接两个门之间的深度扩散区域来增加主体装置的增益。 还公开了一种制造结型场效应晶体管的方法，使得沟道宽度被精确地控制。

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