公开(公告)号：WO2003005622A3

公开(公告)日：2003-01-16

申请号：PCT/US2002/020853

申请日：2002-07-02

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L. ,  STENGEL, Robert, E. ,  BAUTISTA, Edwin, E.

IPC: H04L27/36

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

公开(公告)号：WO1996010865A1

公开(公告)日：1996-04-11

申请号：PCT/US1995012709

申请日：1995-10-02

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  ALFORD, Ronald, C. ,  MARTIN, Frederick, L.

IPC: H03K03/01

CPC classification number: H03K19/017527 ,  H03K19/00369

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies is disclosed which includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode drop below a supply voltage. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract translation: 公开了一种与低电压ECL或CML拓扑结合使用的宽带电平移位电路（200），其包括一个子Vbe电压基准（201），其输出电压偏置了一个低于电源电压的二极管压降的一部分。 比较器电路（203）连接到参考电压电路（201）以及电流源晶体管和差分缓冲电路（205）。 比较器电路（203）将电流源电流晶体管的输出端上的直流电位保持为使来自差分缓冲器的输出信号的共模直流电平从共模直流 宽带交流输入信号的电平。 移位电路（200）提供二极管直流电压降的一小部分的优点，对于从低电源电压工作的电路，AC信号带宽几乎没有损失。

公开(公告)号：WO2005034409A3

公开(公告)日：2005-04-14

申请号：PCT/US2004/032288

申请日：2004-10-01

Applicant: MOTOROLA, INC. ,  GORDAY, Paul, E. ,  CALLAWAY, Edgar, Herbert, Jr. ,  MARTIN, Frederick, L. ,  TAUBENHEIM, David, B.

Inventor： GORDAY, Paul, E. ,  CALLAWAY, Edgar, Herbert, Jr. ,  MARTIN, Frederick, L. ,  TAUBENHEIM, David, B.

IPC: H04B1/18

Abstract: A method (500) and system for compensation of frequency offset between a first transceiver (102) and a second transceiver (104) in wireless communication are disclosed. The compensation of the frequency offset between two or more transceivers (102, 104) is achieved using frequency synchronization bursts. These bursts contain information about the frequency offset. The frequency synchronization bursts are transmitted by the first transceiver at a range of frequencies above and below its carrier frequency (502). A second transceiver that receives at least one of these bursts (504) determines the frequency offset (504), and adjusts its frequency to match the frequency of the first transceiver (508). Thereafter, the second transceiver may enter a low power sleep mode (510) in order to reduce its power consumption. The second transceiver returns to active mode (512) just before the start of the transmission of the data packets (514).

公开(公告)号：WO1993001657A1

公开(公告)日：1993-01-21

申请号：PCT/US1992005578

申请日：1992-07-02

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  MARTIN, Frederick, L. ,  GHOMESHI, Mohammad, M.

IPC: H03L07/00

CPC classification number: H03C3/0983 ,  H03C3/0975 ,  H03L7/185 ,  H03L7/23

Abstract: Briefly, according to the invention, a multi-loop synthesizer (100) for producing an output signal (114) having minimum spurious components is described. The multi-loop synthesizer (100) includes a first synthesizer loop (116) which has a divider stage (108) and an oscillator stage (106) for providing an oscillator output signal (118). The multi-loop synthesizer (100) also includes at least one additional synthesizer loop (121) which also has an output for providing a loop output signal (120). The multi-loop synthesizer (100) further includes an image balanced mixer (110) coupled to the divider stage (108) of the first synthesizer loop for mixing the oscillator output signal (118) of the first synthesizer loop (116) with the loop output (120) of the at least one additional synthesizer loop (121).

公开(公告)号：WO1997009786A1

公开(公告)日：1997-03-13

申请号：PCT/US1996013731

申请日：1996-08-21

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  MARTIN, Frederick, L. ,  CARRALERO, Cesar, W.

IPC: H03L07/08

CPC classification number: H03L7/10 ,  H03J2200/10 ,  H03L7/095 ,  H03L7/099 ,  H03L7/183 ,  Y10S331/02

Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

Abstract translation: 频率合成器（100,500）提供多个可选择的压控振荡器（VCO）频率范围。 VCO控制电路（114）基于VCO阵列（112）或单个可变VCO电路（502）内的所选VCO的锁定条件来控制可选择的VCO频率范围，以向频率合成器（100， 500）。

公开(公告)号：WO1991002405A1

公开(公告)日：1991-02-21

申请号：PCT/US1990003388

申请日：1990-06-18

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  MARTIN, Frederick, L.

IPC: H03D13/00

CPC classification number: H03L7/087

Abstract: A phase detector (20) is provided for detecting the phase difference between a first input signal and a second input signal and providing an output corresponding thereto. The phase detector (20) comprises a dual state phase detector (28), a tri-state phase detector (32), a control input (2) for receiving a control signal, and a control circuit (8, 12, 14 and 16) for selecting either the dual state phase detector (28) or tri-state phase detector (32). The dual state phase detector compares the phase difference between the first input signal and the second input signal. The tri-state phase detector (32) compares the phase difference between the second input signal and the inverse of the first input signal. The control circuit selects the output of the dual state phase detector (28) or selects the output of the tri-state phase detector (32) based upon the control signal.

公开(公告)号：EP0474671B1

公开(公告)日：1995-08-09

申请号：EP90907725.7

申请日：1990-05-17

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L.

IPC: H03D13/00 ,  H03K9/06

CPC classification number: H03D13/004 ,  G01R25/00 ,  H03L7/087

Abstract: A digital phase detector (500) for providing an output (520) characterized by the phase difference of a first input signal (175) and a second input signal (275) is provided. The phase detector comprises a first (200) and a second (300) dual state phase detector, each providing an output having a duty cycle corresponding to the phase difference of the input signals. The phase detectors operate linearly for a range of 360 degrees of phase difference, and provide a signal when the phase difference between the two input signals has exceeded the 360 degree range. The first phase detector (200) provides the phase difference of the first and second input signals, while the second phase detector (300) provides the phase difference between the second and the inverse of the first input signal. The output of the phase detector of the invention is provided by the phase detector having the phase difference within the 360 degree range.

公开(公告)号：EP0629321A1

公开(公告)日：1994-12-21

申请号：EP93906265.0

申请日：1993-02-26

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L.

IPC: H03K19 ,  H03L7

CPC classification number: H03K19/0016 ,  H03L7/18

Abstract: Un circuit électronique (100) comporte un circuit d'étage de charge (116) ayant au moins un TEC (118 et 120). Le circuit à phase de charge (116) comprend une borne de réglage sensible à une tension de réglage pour commander la résistance de la charge du TEC (118 et 120). Le circuit électronique (100) comprend également un générateur de courant de polarisation (124) en vue de générer un courant de polarisation. Un circuit de commande du courant (122) commande la quantité de courant de polarisation appliqué au circuit d'étape de charge (116). Le circuit électronique (100) comprend également une pluralité de bornes de sortie (112 et 114) pour produire une sortie qui est sensible aux tensions appliquées aux bornes d'entrée (104, 106 et 108) du circuit de commande du courant (122). Le circuit (100) permet d'ajuster le courant de polarisation au circuit afin d'obtenir une dissipation de puissance optimum à des conditions de fonctionnement variables.

公开(公告)号：EP0465559A1

公开(公告)日：1992-01-15

申请号：EP90905856.0

申请日：1990-03-26

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L. ,  DAVIS, Darrell, E. ,  SHEPHERD, Wayne, P.

IPC: H03C3 ,  H03L7

CPC classification number: H03C3/0966 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958

Abstract: Un synthétiseur de fréquence (10) produisant un signal de sortie modulé (fo) comprend un signal de fréquence de référence (fr), un oscillateur (14) commandé en tension, un démultiplicateur programmable (6) ainsi qu'un détecteur de phases (12). Un premier intégrateur (24) intégrant un signal de modulation, émet un premier signal de commande. Un second intégrateur (25) couplé audit premier intégrateur (24) émet un second signal de commande. Un différentiateur (36, 42 et 48) couplé audit second intégrateur (25), émet un troisième signal de commande. Enfin, un processeur (41 et 43) traite les premier, second, et troisième signaux de commande, ainsi qu'un code de module (M) du démultiplicateur. Le processeur (41 et 43) couplé audit démultiplicateur programmable modifie le code de module (M) du démultiplicateur en réponse au signal de modulation (9), afin de fournir un diviseur audit démultiplicateur (16), de sorte que la fréquence dudit signal de sortie provenant de l'oscillateur (14) commandé en tension est modulé par ledit signal de modulation (9).

公开(公告)号：EP1444783B1

公开(公告)日：2006-12-27

申请号：EP02773869.9

申请日：2002-10-23

Applicant: MOTOROLA, INC.

Inventor： JUAN, Jui-Kuo ,  STENGEL, Robert, E. ,  MARTIN, Frederick, L. ,  BOCKELMAN, David, E.

IPC: H03L7/07 ,  H03L7/081 ,  H03L7/16 ,  H03H11/26

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.