公开(公告)号：WO1994029870A1

公开(公告)日：1994-12-22

申请号：PCT/US1994004615

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROBINSON, Timothy, B. ,  CAMPBELL, John, G. ,  HANSEN, Craig, C.

IPC: G11C07/00

CPC classification number: G11C7/1039 ,  G11C5/025

Abstract: A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Abstract translation: 大型突发模式存储器（10）访问系统（15）包括N个离散子存储器（11,12）和三个主要I / O端口（17,18,19）。 数据被存储在子存储器中，使得子存储器（11,12）根据其与主I / O端口（17,18,19）的接近度被访问。 三条并行的管道（1,2,3）为主I / O端口（17,18,19）和子存储器（11,12）提供数据路径。 第一管线（1）用于将地址/控制信号耦合到存储器，使得相邻子存储器以半周期间隔被访问。 第二管线（2）用于将访问数据从子存储器传播到主I / O端口，使得每个连续时钟周期从主输出端口输出数据。 第三流水线（3）将写数据传播到存储器，使得在连续时钟周期的第三流水线的输入处呈现的数据被写入连续的子存储器。 冗余电路保留数据完整性，无需存储器访问中断。

公开(公告)号：EP0701733A1

公开(公告)日：1996-03-20

申请号：EP94919985.0

申请日：1994-04-28

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： ROBINSON, Timothy, B. ,  CAMPBELL, John, G. ,  HANSEN, Craig, C.

IPC: G11C11 ,  G11C5 ,  G11C7 ,  G11C29

CPC classification number: G11C7/1039 ,  G11C5/025

Abstract: A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.