公开(公告)号：US12217815B2

公开(公告)日：2025-02-04

申请号：US18055847

申请日：2022-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien Yu Chen

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/36

Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.

公开(公告)号：US20240118964A1

公开(公告)日：2024-04-11

申请号：US17960158

申请日：2022-10-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien Yu Chen ,  Meng-Kai Hsieh

IPC: G06F11/07 ,  H04L41/0631

CPC classification number: G06F11/079 ,  H04L41/0631

Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.

公开(公告)号：US20250166678A1

公开(公告)日：2025-05-22

申请号：US18515257

申请日：2023-11-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien Yu Chen ,  Po-Jen Yang

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

Abstract: A memory device is provided. The memory device includes a first training circuit and a second training circuit. The first training circuit is configured to generate a first clock signal having a first pulse width according a command address (CA) training signal. The second training circuit is coupled to the first training circuit and is configured to adjust the first pulse width of the first clock signal to output a second clock signal having a second pulse width when it is determined that the CA training signal is not enabled.