公开(公告)号：US20250016995A1

公开(公告)日：2025-01-09

申请号：US18219241

申请日：2023-07-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG ,  HSU-CHENG FAN ,  CHIH-YU YEN

IPC: H10B12/00

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

公开(公告)号：US20240121940A1

公开(公告)日：2024-04-11

申请号：US18221538

申请日：2023-07-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHIH-FAN KUAN ,  HSU-CHENG FAN ,  JIANN-JONG WANG ,  CHUNG-HSIN LIN ,  YU-TING LIN

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

公开(公告)号：US20240413007A1

公开(公告)日：2024-12-12

申请号：US18207828

申请日：2023-06-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG ,  HSU-CHENG FAN ,  CHIH-YU YEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.

公开(公告)号：US20240121939A1

公开(公告)日：2024-04-11

申请号：US17963462

申请日：2022-10-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHIH-FAN KUAN ,  HSU-CHENG FAN ,  JIANN-JONG WANG ,  CHUNG-HSIN LIN ,  YU-TING LIN

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

公开(公告)号：US20250016996A1

公开(公告)日：2025-01-09

申请号：US18382683

申请日：2023-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG ,  HSU-CHENG FAN ,  CHIH-YU YEN

IPC: H10B12/00

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

公开(公告)号：US20240413008A1

公开(公告)日：2024-12-12

申请号：US18382199

申请日：2023-10-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG ,  HSU-CHENG FAN ,  CHIH-YU YEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.