公开(公告)号：US20220059355A1

公开(公告)日：2022-02-24

申请号：US17516698

申请日：2021-11-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/285 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/544 ,  H01L27/108

Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

公开(公告)号：US20250132194A1

公开(公告)日：2025-04-24

申请号：US18520114

申请日：2023-11-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

公开(公告)号：US20230352307A1

公开(公告)日：2023-11-02

申请号：US18220963

申请日：2023-07-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/285 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/544 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L21/28506 ,  H01L23/5329 ,  H01L21/3213 ,  H01L23/544 ,  H01L21/7682 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20240339325A1

公开(公告)日：2024-10-10

申请号：US18749899

申请日：2024-06-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/544 ,  H10B12/00

CPC classification number: H01L21/28506 ,  H01L21/3213 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/544 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20240055261A1

公开(公告)日：2024-02-15

申请号：US18383158

申请日：2023-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/285 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/544 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L21/28506 ,  H01L23/5329 ,  H01L21/3213 ,  H01L23/544 ,  H01L21/7682 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20230386558A1

公开(公告)日：2023-11-30

申请号：US17824011

申请日：2022-05-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4085 ,  G11C11/4097

Abstract: The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.

公开(公告)号：US20220189847A1

公开(公告)日：2022-06-16

申请号：US17685544

申请日：2022-03-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L23/373 ,  H01L21/02 ,  H01L23/00

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm2/Watt and about 0.25° C. cm2/Watt.

公开(公告)号：US20220157713A1

公开(公告)日：2022-05-19

申请号：US17550354

申请日：2021-12-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L23/522 ,  H01L21/768

Abstract: The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

公开(公告)号：US20250132193A1

公开(公告)日：2025-04-24

申请号：US18381907

申请日：2023-10-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

公开(公告)号：US20230389282A1

公开(公告)日：2023-11-30

申请号：US17824507

申请日：2022-05-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L27/108

CPC classification number: H01L27/10811 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10885

Abstract: The present disclosure provides a method for preparing a memory device. The method includes forming a first bottom cell within a bottom substrate, comprising: forming a first bottom capacitor within the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line. The method also includes forming a first top cell within a top substrate, comprising: forming a first top capacitor within the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first top channel layer surrounded by the first top word line. The method further includes forming a common bit line between the first bottom cell and the first top cell and extending along a second direction substantially perpendicular to the first direction.