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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210104525A1

    公开(公告)日：2021-04-08

    申请号：US16592784

    申请日：2019-10-04

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H01L27/108 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/764 ,  H01L29/66

    Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250133718A1

    公开(公告)日：2025-04-24

    申请号：US18489459

    申请日：2023-10-18

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H10B12/00

    Abstract: A semiconductor device includes a bit line, a source, a body, a channel, a drain, a word line and a first body contact. The source is on the bit line. The body is on the source. The channel is on the body. The drain is on the channel. The word line surrounds and is spaced apart from the channel. The first body contact is on the body, in which the first body contact and the source are separated by the body.

    MEMORY STRUCTURE
    4.
    发明公开
    MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20240032278A1

    公开(公告)日：2024-01-25

    申请号：US17814235

    申请日：2022-07-22

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H01L27/108

    CPC classification number: H01L27/10823

    Abstract: A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250089240A1

    公开(公告)日：2025-03-13

    申请号：US18244242

    申请日：2023-09-09

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H10B12/00

    Abstract: A manufacturing method of a memory device includes forming a capacitor in a first dielectric layer, and forming a bottom electrode over the capacitor. A word line and a second dielectric layer are formed over the bottom electrode and the first dielectric layer, in which the word line is embedded in the second dielectric layer. A bit line contact is formed over the second dielectric layer, in which a vertical projection of the bit line contact on the first dielectric layer is spaced apart a vertical projection of the bottom electrode on the first dielectric layer. After forming the bit line contact, a channel in contact with the bottom electrode and the word line is formed. A top electrode is formed over the channel and in contact with the bit line contact.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240298437A1

    公开(公告)日：2024-09-05

    申请号：US18177102

    申请日：2023-03-01

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H10B12/00

    CPC classification number: H10B12/488 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor device includes a substrate, a first word line, a barrier layer, a first insulating layer and a second insulating layer. The first word line is in the substrate. The barrier layer cups an underside of the first word line. The first insulating layer extends along a top surface of the first word line and is laterally surrounded by the barrier layer. The second insulating layer is on the first insulating layer and laterally surrounded by the barrier layer. The second insulating layer has a material different from a material of the first insulating layer.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220344507A1

    公开(公告)日：2022-10-27

    申请号：US17811588

    申请日：2022-07-11

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Yu-Ping CHEN ,  Jhen-Yu TSAI

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.

    MEMORY DEVICE AND METHOD OF FORMING THE SAME
    10.
    发明申请
    MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220068924A1

    公开(公告)日：2022-03-03

    申请号：US17002765

    申请日：2020-08-25

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Jhen-Yu TSAI

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A memory device includes a substrate, a conductive line, a capacitor, a transistor, and a contact structure. The conductive line is above a peripheral region of the substrate. The capacitor is above a memory region of the substrate. The transistor is above and connected to the capacitor and includes first and second source/drain regions, a channel, and a gate structure. The first source/drain region is connected to the capacitor. The gate structure laterally surrounds the channel. The contact structure is above the peripheral region and includes a bottom portion, a top portion, and a middle portion. The bottom portion is connected to the conductive line. The top portion is connected to the second source/drain region. The middle portion is wider than the top portion and the bottom portion, in which the middle portion of the contact structure is at a height substantially level with the gate structure.

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