公开(公告)号：US20230157006A1

公开(公告)日：2023-05-18

申请号：US17528617

申请日：2021-11-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

公开(公告)号：US20220139777A1

公开(公告)日：2022-05-05

申请号：US17573793

申请日：2022-01-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/528

Abstract: A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

公开(公告)号：US20250140651A1

公开(公告)日：2025-05-01

申请号：US18520955

申请日：2023-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

公开(公告)号：US20230156999A1

公开(公告)日：2023-05-18

申请号：US17528505

申请日：2021-11-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876

Abstract: A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

公开(公告)号：US20220093575A1

公开(公告)日：2022-03-24

申请号：US17537972

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00

Abstract: The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

公开(公告)号：US20250140749A1

公开(公告)日：2025-05-01

申请号：US18520946

申请日：2023-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.

公开(公告)号：US20250140646A1

公开(公告)日：2025-05-01

申请号：US18385504

申请日：2023-10-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

公开(公告)号：US20240153772A1

公开(公告)日：2024-05-09

申请号：US18396818

申请日：2023-12-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

公开(公告)号：US20250140747A1

公开(公告)日：2025-05-01

申请号：US18385499

申请日：2023-10-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.

公开(公告)号：US20230371230A1

公开(公告)日：2023-11-16

申请号：US18221535

申请日：2023-07-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.