公开(公告)号：US20230420307A1

公开(公告)日：2023-12-28

申请号：US17808917

申请日：2022-06-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/66 ,  C23C16/52

CPC classification number: H01L22/12 ,  C23C16/52

Abstract: A deposition method includes executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range. The second deposition recipe is generated taking into consideration at least one of a deposition rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and an implanting recipe of the first wafer. The second deposition recipe is configured to be applied on a second wafer to be processed after the first wafer.

公开(公告)号：US20230420306A1

公开(公告)日：2023-12-28

申请号：US17808912

申请日：2022-06-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/66 ,  H01L21/265

CPC classification number: H01L22/12 ,  H01L21/265

Abstract: An implanting method includes executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The second implanting recipe is generated taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and a deposition recipe of the first wafer. The second implanting recipe is configured to be applied on a second wafer to be processed after the first wafer.

公开(公告)号：US20220093533A1

公开(公告)日：2022-03-24

申请号：US17538090

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L23/64 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48

Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer;

公开(公告)号：US20230418259A1

公开(公告)日：2023-12-28

申请号：US17808940

申请日：2022-06-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: G05B19/4099

CPC classification number: G05B19/4099 ,  G05B2219/45031

Abstract: An etching method includes executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The second etching recipe is generated taking into consideration at least one of an etching rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an implanting recipe of the first wafer, and a deposition recipe of the first wafer. The second etching recipe is configured to be applied on a second wafer to be processed after the first wafer.

公开(公告)号：US20230360978A1

公开(公告)日：2023-11-09

申请号：US17735293

申请日：2022-05-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/66 ,  H01L21/02

CPC classification number: H01L22/26 ,  H01L22/12 ,  H01L22/14 ,  H01L21/0201 ,  G06N20/20

Abstract: The present application discloses a method for controlling an implanting tool. The method includes executing a first implantation recipe on a current wafer; generating a first set of data of the current wafer by a first measurement module; analyzing the first set of data by an artificial intelligence module coupled to the first measurement module; generating, by the artificial intelligence module, a second implantation recipe and applying the second implantation recipe to the implantation tool when the first set of data is not within a predetermined range; and executing the second implantation recipe on a next wafer.

公开(公告)号：US20240249975A1

公开(公告)日：2024-07-25

申请号：US18598173

申请日：2024-03-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H10B12/00

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H10B12/00

Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap. A second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

公开(公告)号：US20230345707A1

公开(公告)日：2023-10-26

申请号：US17729250

申请日：2022-04-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/10885 ,  H01L21/76811 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53209 ,  H01L23/53295

Abstract: The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

公开(公告)号：US20230260830A1

公开(公告)日：2023-08-17

申请号：US17670751

申请日：2022-02-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L27/108

Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

公开(公告)号：US20240258159A1

公开(公告)日：2024-08-01

申请号：US18632542

申请日：2024-04-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H10B12/00

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H10B12/00

Abstract: A semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

公开(公告)号：US20240088020A1

公开(公告)日：2024-03-14

申请号：US18508581

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TZU-CHING TSAI

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.