公开(公告)号：US12278183B2

公开(公告)日：2025-04-15

申请号：US17740527

申请日：2022-05-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a first insulating layer positioned on a substrate; a bottom contact positioned in the first insulating layer; a bottom dielectric layer, a lower middle dielectric layer, a higher middle dielectric layer, and a top dielectric layer sequentially stacked on the first insulating layer; and a conductive structure including a bottom portion positioned in the bottom dielectric layer and on the bottom contact, a lower middle portion positioned on the bottom portion and in the lower middle dielectric layer, a higher middle portion positioned on the lower middle portion and in the higher middle dielectric layer, and a top portion positioned on the higher middle portion and in the top dielectric layer. A carbon concentration of the lower middle dielectric layer is greater than a carbon concentration of the bottom dielectric layer.

公开(公告)号：US12113028B2

公开(公告)日：2024-10-08

申请号：US17556149

申请日：2021-12-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/8313 ,  H01L2225/06593

Abstract: The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

公开(公告)号：US12094833B2

公开(公告)日：2024-09-17

申请号：US17676999

申请日：2022-02-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/544 ,  H01L21/68

CPC classification number: H01L23/544 ,  H01L21/68 ,  H01L2223/54426

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first subset of solid alignment marks positioned over a substrate and including: a first-layer-alignment mark positioned on the substrate, and a second-layer-alignment mark positioned above and deviated from the first-layer-alignment mark of the first subset of solid alignment marks; and a first subset of spaced alignment marks positioned over the substrate, distant from the first subset of solid alignment marks, and including: a first-layer-alignment mark positioned on the substrate and distant from the first-layer-alignment mark of the first subset of solid alignment marks, and a second-layer-alignment mark positioned above and deviated from the first-layer-alignment mark of the first subset of spaced alignment marks. The first subset of solid alignment marks and the first subset of spaced alignment marks include a fluorescence material.

公开(公告)号：US12027480B2

公开(公告)日：2024-07-02

申请号：US18378885

申请日：2023-10-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/488 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/4828 ,  H01L23/488 ,  H01L23/53238

Abstract: A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.

公开(公告)号：US11901350B2

公开(公告)日：2024-02-13

申请号：US17563346

申请日：2021-12-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a first stacking structure comprising a first controller die, and a plurality of first storage dies sequentially stacked on the first controller die; providing a second stacking structure comprising a second controller die, and a plurality of second storage dies sequentially stacked on the second controller die; bonding the first controller die onto a bottom die through a plurality of first interconnect units; and bonding the second controller die onto the bottom die through a plurality of second interconnect units. The plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array. The plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.

公开(公告)号：US11823984B2

公开(公告)日：2023-11-21

申请号：US17497775

申请日：2021-10-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/485 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.

公开(公告)号：US11791399B2

公开(公告)日：2023-10-17

申请号：US17516690

申请日：2021-11-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/6656 ,  H01L29/4916 ,  H01L29/515

Abstract: The present application discloses a method for fabricating semiconductor device with a graphene-based element. The method includes providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.

公开(公告)号：US11735527B2

公开(公告)日：2023-08-22

申请号：US17517549

申请日：2021-11-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/532 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L23/5329 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: The present application discloses a semiconductor device with a graded porous dielectric structure. The semiconductor device includes a substrate; two conductive features positioned apart from each other over the substrate, a graded porous dielectric structure positioned between the two conductive features; and a dielectric layer positioned between one of the two conductive features and the graded porous dielectric structure; wherein the graded porous dielectric structure comprises a first portion having a first porosity and a second portion having a second porosity, and the second porosity is higher than the first porosity.

公开(公告)号：US11678480B2

公开(公告)日：2023-06-13

申请号：US17537955

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H10B12/485 ,  H01L21/7682 ,  H01L23/5329 ,  H10B12/053 ,  H10B12/34 ,  H01L2221/1047

Abstract: The present application discloses a method for fabricating the semiconductor device with the porous decoupling features. The method includes providing a substrate; integrally forming a first conductive line and a bottom contact on the substrate; integrally forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact; and forming a porous insulating layer between the first conductive line spacer and the bottom contact spacer.

公开(公告)号：US11631637B2

公开(公告)日：2023-04-18

申请号：US17751948

申请日：2022-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48

Abstract: The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.