公开(公告)号：US12237370B2

公开(公告)日：2025-02-25

申请号：US18382673

申请日：2023-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L29/06 ,  H10B12/00

Abstract: The present disclosure provides a semiconductor device includes a semiconductor substrate, a first metal plug, a second metal plug, a third metal plug, a fourth metal plug, and a boron nitride layer. The first metal plug and the second metal plug are disposed over a pattern-dense region of the semiconductor substrate. The third metal plug and the fourth metal plug are disposed over a pattern-loose region of the semiconductor substrate. The boron nitride layer is disposed over the semiconductor substrate. Each of the first metal plug and the second metal plug includes a barrier layer and a conductive feature. The barrier layer is contact with the semiconductor substrate. The conductive feature is disposed over the barrier layer. The conductive feature is separated from the semiconductor substrate by the barrier layer.

公开(公告)号：US11785757B2

公开(公告)日：2023-10-10

申请号：US17528490

申请日：2021-11-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method for preparing the memory are provided. The method includes forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively.

公开(公告)号：US11380758B2

公开(公告)日：2022-07-05

申请号：US16937347

申请日：2020-07-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L29/06 ,  H01L27/108

Abstract: The present disclosure provides a semiconductor device with an air gap and a boron nitride cap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a boron nitride layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the boron nitride layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

公开(公告)号：US11742382B2

公开(公告)日：2023-08-29

申请号：US17537911

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L29/06 ,  H10B12/00

CPC classification number: H01L29/0649 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/31

Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a boron nitride layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the boron nitride layer extends between the first metal plug and the second metal plug such that the first portion of the boron nitride layer and the semiconductor substrate are separated by an airgap while a second portion of the boron nitride layer extends between the third metal plug and the fourth metal plug such that the second portion of the boron nitride layer is in direct contact with the semiconductor substrate.

公开(公告)号：US12245431B2

公开(公告)日：2025-03-04

申请号：US18383146

申请日：2023-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522

Abstract: The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor patterns structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.

公开(公告)号：US12114476B2

公开(公告)日：2024-10-08

申请号：US18221534

申请日：2023-07-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method for preparing the memory are provided. The method includes forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively.

公开(公告)号：US11610899B2

公开(公告)日：2023-03-21

申请号：US17347924

申请日：2021-06-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L27/108

Abstract: The present application provides a memory cell, a memory array and a method for preparing the memory cell. The memory cell includes an active area, an isolation structure and a contact enhancement layer. The active area is a surface portion of a semiconductor substrate. A top surface of the active area has a slop part descending toward an edge of the active area within a peripheral region of the active area. The isolation structure is formed in a trench of the semiconductor substrate laterally surrounding the active area. The contact enhancement layer covers the edge of the active area and in lateral contact with the isolation structure. The slope part of the top surface of the active area is covered by the contact enhancement layer, and the contact enhancement layer is formed of a semiconductor material.

公开(公告)号：US10916639B1

公开(公告)日：2021-02-09

申请号：US16511602

申请日：2019-07-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78

Abstract: The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.

公开(公告)号：US11877455B2

公开(公告)日：2024-01-16

申请号：US17538106

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B43/27 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522

CPC classification number: H10B43/27 ,  H01L21/7682 ,  H01L23/5329 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/31127 ,  H01L23/5226

Abstract: The present disclosure provides a method for preparing a vertical memory structure with air gaps. The method includes providing a substrate; forming an impurity layer at an upper portion of the substrate; forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.

公开(公告)号：US11411019B2

公开(公告)日：2022-08-09

申请号：US16848359

申请日：2020-04-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522

Abstract: The present disclosure provides a vertical memory structure with air gaps and a method for preparing the vertical memory structure. The vertical memory structure includes a semiconductor stack including a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.