公开(公告)号：JPS6091711A

公开(公告)日：1985-05-23

申请号：JP20033883

申请日：1983-10-26

Applicant: NAT AEROSPACE LAB

Inventor： TADA AKIRA

IPC: H03H17/00 ,  H03H17/02 ,  H03H17/06

Abstract: PURPOSE:To attain sampling while eliminating aliasing by repeating an integral number of stages of processings comprising the moving average processing using binomial coefficients used as weights for a quantized discrete time series data and the processing extracting data in the rate of 1/2. CONSTITUTION:In a fundamental processing circuit 11, a clock signal 2 stores an inputted odd number order of discrete signal to a memory M1 and clock signal 1 sotres an inputted even number order of discrete signal to a memory M2. An output of the memory M1 is used as an input to a full adder FA1 and an output of the memory M2 is used for an input to the full adder FA1 while being weighted by a binomial coefficient. An output of the full adder FA1 and the discrete signal are added at a full adder FA2, and the result is multiplied by 1/4, then a sample signal is obtained. Similar processings are conducted also in a fundamental processing circuit 12, the sample signal is extracted sequentially in the rate of 50% at higher stages and the filtering digital smapling is executed without being affected by aliasing.