公开(公告)号：WO1980002760A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000666

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  AMACHER G ,  NASEEM S

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol decoding system incorporated in a NMOS/LSI chip (24) generates asynchronously binary data in response to the scanning of bars and spaces of the symbol. The binary data may represent each bar or space as a numerical character, a margin or a center band of the symbol. The binary data also includes data identifying respective bars and spaces (MARK) and if the character generated is valid or invalid (EQUAL). The validity signal is generated by comparing a count derived from scanning four consecutive intervals with the count from scanning the previous four consecutive intervals. Logic circuits (52, 56, 60) generate a time delay period allowing the binary data to be generated asynchronously during the delay period. At the end of the delay period the binary data is outputted to a utilizing device (28) for selecting the valid data from the data outputted by the decoding system.

公开(公告)号：WO1980002759A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000665

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  NASEEM S ,  AMACHER G ,  BLANFORD D

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips (22, 24, 28, 30) generates data representing numerical characters encoded in the symbol. Scanning means (20) generates signals (RTV, STV) in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip (24) as valid and invalid characters, the valid characters being recognized by a second chip (28) which stores the valid characters and enables a microprocessor chip (30) to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip (30).