公开(公告)号：WO1980002759A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000665

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  NASEEM S ,  AMACHER G ,  BLANFORD D

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips (22, 24, 28, 30) generates data representing numerical characters encoded in the symbol. Scanning means (20) generates signals (RTV, STV) in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip (24) as valid and invalid characters, the valid characters being recognized by a second chip (28) which stores the valid characters and enables a microprocessor chip (30) to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip (30).

公开(公告)号：WO1980002758A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000664

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  BLANFORD D ,  NASEEM S

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol processing system incorporated in an NMOS/LSI chip separates valid data from invalid data all generated by scanning a bar-coded symbol. The signals representing the bars and spaces of the symbol are decoded by a pattern recognition array (24), and the decoded data is clocked into a storage unit (81-84). When valid data is discovered, such data is captured within the storage unit. The valid data is then clocked out of the storage unit to a utilization device (30) for further processing.