公开(公告)号：WO1980001119A1

公开(公告)日：1980-05-29

申请号：PCT/US1979000989

申请日：1979-11-16

Applicant: NCR CORP

Inventor： NCR CORP ,  CRAYCRAFT D

IPC: G11C17/00

CPC classification number: H01L27/112 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5692 ,  G11C17/12

Abstract: A read-only memory includes an array of field effect transistors (111, 112, ..., mk). Each field effect transistor has a channel width selected from 2 s possible widths (n > 1) to provide one of 2 s possible output voltages upon sensing. The output voltage is applied to a set of 2 s - 1 sense amplifiers, each of which is selectively activated at a separate one of 2 s - 1 voltage levels intermediate two adjacent values of the 2 s output voltages. The sense amplifier outputs drive a logic circuit (104) providing n binary outputs, one of which may be selected by a decoder (105).

Abstract translation: 只读存储器包括场效应晶体管（111,112，...，mk）的阵列。 每个场效应晶体管具有从2ns的可能宽度（n> 1）中选择的沟道宽度，以在感测时提供2个可能的输出电压之一。 输出电压被施加到一组2ns-1个读出放大器，每个读出放大器被选择性地以两个相邻的两个相邻值之间的2个s-1电压电平中的一个单独的一个激活 输出电压。 读出放大器输出驱动提供n个二进制输出的逻辑电路（104），其中之一可由解码器（105）选择。

公开(公告)号：WO1981001483A1

公开(公告)日：1981-05-28

申请号：PCT/US1980001518

申请日：1980-11-10

Applicant: NCR CORP

Inventor： NCR CORP ,  LOCKWOOD G ,  DONALDSON D ,  CRAYCRAFT D

IPC: G11C11/40

CPC classification number: G11C14/00

Abstract: A volatile/non-volatile RAM cell (400) employing a bistable multivibrator with non-volatile, alterable-threshold capacitors (407, 408) coupled to the output terminals (A, B) thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section (A) and an alterable section (B), the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors (409, 410) of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes (C, D). The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.