Abstract:
A computer system having enhancement circuitry for memory accessing, and has particular application to a system in which the number of bits which can be processed at one time by the processor is less than the number of bits in either a data word stored in the memory or the address associated with it. In a computer system (10) in accordance with the invention, enhancement circuitry (42) is connected between two buses (18, 20) which respectively connect a microprocessor (12) to a main memory (14) and to peripheral subsystems (16). The microprocessor is arranged to fetch a data word in said memory by loading an address in address registers (50, 54, 58, 62, 66) included in said enhancement circuitry (42) and is arranged to store a data word in said memory by loading an address in said address registers and a data word in data registers (52, 56, 60, 64, 68) also included in said enhancement circuitry.