公开(公告)号：WO1980001425A1

公开(公告)日：1980-07-10

申请号：PCT/US1979001141

申请日：1979-12-28

Applicant: NCR CORP

Inventor： NCR CORP ,  PATEL N

IPC: G11C07/00

CPC classification number: G11C11/4072 ,  G11C11/406

Abstract: A circuit which efficiently controls the refresh operation of a dynamic memory. The refresh control circuit operates such that a dynamic memory (28) coupled to a processing means responds to a memory access signal (BMREQ) for a read/write operation and a first refresh control signal (BMREF) for a memory refresh operation. First circuits (30, 32) provide a second periodic refresh control signal (REFREQ), and second circuits (34, 40) refresh the memory under the control of either of the first (BMREF) or second (REFREQ) refresh control signals. A third circuit (20) responsive to the memory access signal (BMREQ) and the second refresh control signal (REFREQ) awards priority of access to the memory (28) in accordance with the first active signal which it receives. A fourth circuit (20) puts the processing means in a hold condition when priority is awarded to the second refresh control signal (REFREQ). In a power down condition a (BRST) signal enables gates (42) having a battery back up to permit the dynamic memory to be refreshed.

Abstract translation: 一种有效地控制动态存储器的刷新操作的电路。 刷新控制电路的操作使得耦合到处理装置的动态存储器（28）响应用于读/写操作的存储器访问信号（BMREQ）和用于存储器刷新操作的第一刷新控制信号（BMREF）。 第一电路（30,32）提供第二周期性刷新控制信号（REFREQ），第二电路（34,40）在第一（BMREF）或第二（REFREQ）刷新控制信号中的任一个的控制下刷新存储器。 响应于存储器访问信号（BMREQ）和第二刷新控制信号（REFREQ）的第三电路（20）根据接收到的第一有效信号来授予对存储器（28）的访问的优先级。 当优先权被授予第二刷新控制信号（REFREQ）时，第四电路（20）将处理装置置于保持状态。 在断电状态下，（BRST）信号使得具有电池备份的门（42）能够刷新动态存储器。

公开(公告)号：WO1980001424A1

公开(公告)日：1980-07-10

申请号：PCT/US1979001126

申请日：1979-12-27

Applicant: NCR CORP

Inventor： NCR CORP ,  PATEL N

IPC: G06F13/00

CPC classification number: G06F12/0864

Abstract: A memory system comprises a pair of RAM buffer memories (22, 24) coupled to a CCD main memory (20) to provide high-speed memory access to the memory by a processing means. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Comparison means (76, 78) included in the system compares the page address in a memory request with the page address, located in address registers, of the data stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for a read/write operation at the addressed memory location. If no comparison is found, circuits (72, 92, 134) using the requested page address transfer the page in which the requested address is located from the CCD main memory to a RAM buffer memory for access by the processing means; the buffer memory to which the page is transferred is the buffer memory that was not accessed in the immediately preceding memory request. If a write operation had occured on a page stored in the buffer memories, the altered page is transferred back to the CCD main memory before a new page of data is transferred to the buffer memory.

Abstract translation: 存储器系统包括耦合到CCD主存储器（20）的一对RAM缓冲存储器（22,24），以通过处理装置向存储器提供高速存储器访问。 每个缓冲存储器中存储有从CCD主存储器传送的数据页。 包括在系统中的比较装置（76,78）将存储器请求中的页面地址与存储在缓冲存储器中的数据的地址寄存器中的页面地址进行比较。 如果发现比较，则在指定的存储器位置访问指定的缓冲存储器用于读/写操作。 如果没有发现比较，使用请求的页地址的电路（72,92,134）将请求的地址所在的页面从CCD主存储器传送到RAM缓冲存储器，以供处理装置访问; 页面传输到的缓冲存储器是在前一个存储器请求中未被访问的缓冲存储器。 如果在存储在缓冲存储器中的页面上发生了写入操作，则在新的数据页被传送到缓冲存储器之前，改变的页面被传送回到CCD主存储器。

公开(公告)号：WO1979000959A1

公开(公告)日：1979-11-15

申请号：PCT/US1979000228

申请日：1979-04-12

Applicant: NCR CORP

Inventor： NCR CORP ,  ROBERTS J ,  JEFFS P ,  PATEL N

IPC: G06F09/06

CPC classification number: G06F12/04

Abstract: A computer system having enhancement circuitry for memory accessing, and has particular application to a system in which the number of bits which can be processed at one time by the processor is less than the number of bits in either a data word stored in the memory or the address associated with it. In a computer system (10) in accordance with the invention, enhancement circuitry (42) is connected between two buses (18, 20) which respectively connect a microprocessor (12) to a main memory (14) and to peripheral subsystems (16). The microprocessor is arranged to fetch a data word in said memory by loading an address in address registers (50, 54, 58, 62, 66) included in said enhancement circuitry (42) and is arranged to store a data word in said memory by loading an address in said address registers and a data word in data registers (52, 56, 60, 64, 68) also included in said enhancement circuitry.