公开(公告)号：WO1981001893A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001663

申请日：1980-12-09

Applicant: NCR CORP

Inventor： NCR CORP ,  KOCOL J ,  SCHUCK D

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A self-correcting memory system (10) includes internal error detection and correction circuitry (20) that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system (10). The error detection and correction circuitry (20) includes an ECC checking circuit (36) that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter (44) is cascaded to a refresh address counter (42) in the control circuitry (41) of the memory system (10) so that the accessing of each data word occurs during a refresh cycle of the memory system (10).