公开(公告)号：WO1981001893A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001663

申请日：1980-12-09

Applicant: NCR CORP

Inventor： NCR CORP ,  KOCOL J ,  SCHUCK D

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A self-correcting memory system (10) includes internal error detection and correction circuitry (20) that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system (10). The error detection and correction circuitry (20) includes an ECC checking circuit (36) that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter (44) is cascaded to a refresh address counter (42) in the control circuitry (41) of the memory system (10) so that the accessing of each data word occurs during a refresh cycle of the memory system (10).

公开(公告)号：WO1980000043A1

公开(公告)日：1980-01-10

申请号：PCT/US1979000402

申请日：1979-06-07

Applicant: NCR CORP

Inventor： NCR CORP ,  MARRO D ,  SCHUCK D

IPC: G06F07/00

CPC classification number: G06F9/3867

Abstract: A digital pipelined computer includes a memory (10) arranged to store high level language instructions and a plurality of microprogrammed digital computers (11, 12, 13, 14) coupled in parallel to the memory (10) and intercoupled by an interface (19) to form a pipeline for executing the high level language instructions. The interface (19) includes buffer register means (20-25) connected between selected pairs of the microprogrammed digital computers. When one of the microprogrammed digital computers attempts to load a full buffer register means or to read an empty buffer register means the computer initiating such attempt is temporarily halted.

Abstract translation: 数字流水线计算机包括被布置为存储高级语言指令的存储器（10）和并联耦合到存储器（10）并且由接口（19）相互配合的多个微程序数字计算机（11,12,13,14） 以形成用于执行高级语言指令的流水线。 接口（19）包括连接在选择的微程序数字计算机对之间的缓冲寄存器装置（20-25）。 当微程序数字计算机之一尝试加载完整的缓冲寄存器装置或读取空的缓冲寄存器时，暂时停止启动此类尝试的计算机。