公开(公告)号：WO1979000912A1

公开(公告)日：1979-11-15

申请号：PCT/US1978000084

申请日：1978-09-19

Applicant: NCR CORP

Inventor： NCR CORP ,  LAUFFER D ,  WARD W

IPC: G11C11/40

CPC classification number: G06F13/4243 ,  G11C5/00 ,  G11C5/066

Abstract: A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.

Abstract translation: 用于减少存储器件上的外部引脚或端子数量的电路包括周期性地使第一外部引脚上的信号提供给存储器件内部电源的电源端的计数器电路，并且在相同 时间，将第二外部引脚上的接地电平信号提供给内部电源的接地端子。 在接收两个外部引脚上的信号的其他时间，第一个引脚上的信号提供存储器选择和时钟功能，第二个引脚上的信号提供存储模式选择，地址和数据输入和输出功能。

公开(公告)号：WO1979000914A1

公开(公告)日：1979-11-15

申请号：PCT/US1979000178

申请日：1979-03-19

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W ,  LAUFFER D

IPC: G11C11/40

CPC classification number: G11C19/282 ,  G06F13/4243 ,  G11C5/00 ,  G11C5/066 ,  G11C19/287 ,  H03K17/302 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device (10) includes a circuit for reducing the number of pins or external terminals on the memory device (10). A threshold detector (49) within the circuit detects the difference in voltage between signals applied at two external pins (C u, F u). A clocking signal at one pin (C u) provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin (F u) provides memory mode select as well as memory address, data input and data output functions. Switching transistors (24, 28) controlled by the output of the threshold detector (40) connect the external pins (C u, F u) to the power and ground terminals of an internal power supply (16) so that the signals at the two external pins (C u, F u) also provide the power and ground signals to the memory device (10).

Abstract translation: 存储器件（10）包括用于减少存储器件（10）上的引脚数量或外部端子的电路。 电路内的阈值检测器（49）检测在两个外部引脚（C u，u u）处施加的信号之间的电压差。 一个引脚（C uu u）的时钟信号除了同步功能外，还提供存储器件选择功能，另一个引脚（F uu u）上的信号提供存储器模式选择以及存储器 地址，数据输入和数据输出功能。 由门限检测器（40）的输出控制的开关晶体管（24,28）将外部引脚（C u，F u）连接到内部电源（16）的电源和接地端子，从而 两个外部引脚（C u，u u u u）处的信号也向存储器件（10）提供电源和接地信号。