公开(公告)号：WO1980000632A1

公开(公告)日：1980-04-03

申请号：PCT/US1979000675

申请日：1979-08-28

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W

IPC: G11C13/00

CPC classification number: G11C11/414 ,  G06F13/4243 ,  G11C7/22 ,  G11C11/409 ,  Y02D10/14 ,  Y02D10/151

Abstract: A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.

公开(公告)号：WO1980000626A1

公开(公告)日：1980-04-03

申请号：PCT/US1979000669

申请日：1979-08-27

Applicant: NCR CORP

Inventor： NCR CORP ,  LEWIS W ,  WARD W

IPC: G06F11/12

CPC classification number: H03M13/19

Abstract: A data processing system (10) implemented in LSI includes a plurality of identical error detection and correction (EDC) circuits (30a-f) operating either in an error correction code (ECC) mode by generating ECC parity bits, or a byte parity mode by generating or checking byte parity bits. In operation in an ECC mode, the EDC circuit (30a) generates ECC check bits for storage in association with a data word being stored in a memory (14). When a data word is fetched from the memory (14) the fetched check bits are compared with check bits generated by the EDC circuit (30a) in an error control circuit (36) to provide syndrome bits. For a single error the syndrome bits cause the provision of an enable signal to that one of a plurality of memory interface circuits (13a-d) containing the error, all the interface circuits (13a-d) being provided with identical syndrome bits identifying a bit position within the interface circuit. The EDC circuits (30) may be used individually with a 32 bit data bus or may be combined for use with a 64 bit data bus.

公开(公告)号：WO1979000914A1

公开(公告)日：1979-11-15

申请号：PCT/US1979000178

申请日：1979-03-19

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W ,  LAUFFER D

IPC: G11C11/40

CPC classification number: G11C19/282 ,  G06F13/4243 ,  G11C5/00 ,  G11C5/066 ,  G11C19/287 ,  H03K17/302 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device (10) includes a circuit for reducing the number of pins or external terminals on the memory device (10). A threshold detector (49) within the circuit detects the difference in voltage between signals applied at two external pins (C u, F u). A clocking signal at one pin (C u) provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin (F u) provides memory mode select as well as memory address, data input and data output functions. Switching transistors (24, 28) controlled by the output of the threshold detector (40) connect the external pins (C u, F u) to the power and ground terminals of an internal power supply (16) so that the signals at the two external pins (C u, F u) also provide the power and ground signals to the memory device (10).

Abstract translation: 存储器件（10）包括用于减少存储器件（10）上的引脚数量或外部端子的电路。 电路内的阈值检测器（49）检测在两个外部引脚（C u，u u）处施加的信号之间的电压差。 一个引脚（C uu u）的时钟信号除了同步功能外，还提供存储器件选择功能，另一个引脚（F uu u）上的信号提供存储器模式选择以及存储器 地址，数据输入和数据输出功能。 由门限检测器（40）的输出控制的开关晶体管（24,28）将外部引脚（C u，F u）连接到内部电源（16）的电源和接地端子，从而 两个外部引脚（C u，u u u u）处的信号也向存储器件（10）提供电源和接地信号。

公开(公告)号：WO1980000633A1

公开(公告)日：1980-04-03

申请号：PCT/US1979000660

申请日：1979-08-23

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W

IPC: G11C19/28

CPC classification number: G11C19/36 ,  G11C19/285

Abstract: A data storage system (10) for storing multilevel, non-binary data includes a charge coupled device shift register (12) and a detection circuit (20) for detecting the data level represented by the charge or signal within each cell location of the shift register (12). The detection circuit (20) includes a sense amplifier (30) for comparing the signals from two adjacent cell locations (b0, b1), with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors (50, 52) cause the output of an incrementing digital-to-analog converter (40) to be added to one of the signals prior to comparison. The output of the sense amplifier (30) is provided to a flip-flop (32), which controls the switching transistors (50, 52). The outputs of the sense amplifier (30) and flip-flop (32) are connected to an EXCLUSIVE NOR gate (54), whose output enables an up/down counter (56), which in turn provides a detected data level.

公开(公告)号：WO1980000387A1

公开(公告)日：1980-03-06

申请号：PCT/US1979000565

申请日：1979-07-31

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W

IPC: G11C19/28

CPC classification number: G11C19/285

Abstract: A data storage system (10) includes a charge coupled device shift register (12) and a detection circuit (20) for detecting the binary value represented by the charge level or signal within each cell location of the shift register. The detection circuit (20) includes a sense amplifier (30) for comparing the signals from two adjacent cell locations (b0, b1), with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors (40, 42) cause an adjustment voltage (Va) to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop (32), which controls the switching transistors and is set to a predetermined state whenever a reference data item is located in the cell location (b0) providing the signal representing the known binary value.

公开(公告)号：WO1979000912A1

公开(公告)日：1979-11-15

申请号：PCT/US1978000084

申请日：1978-09-19

Applicant: NCR CORP

Inventor： NCR CORP ,  LAUFFER D ,  WARD W

IPC: G11C11/40

CPC classification number: G06F13/4243 ,  G11C5/00 ,  G11C5/066

Abstract: A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.

Abstract translation: 用于减少存储器件上的外部引脚或端子数量的电路包括周期性地使第一外部引脚上的信号提供给存储器件内部电源的电源端的计数器电路，并且在相同 时间，将第二外部引脚上的接地电平信号提供给内部电源的接地端子。 在接收两个外部引脚上的信号的其他时间，第一个引脚上的信号提供存储器选择和时钟功能，第二个引脚上的信号提供存储模式选择，地址和数据输入和输出功能。