公开(公告)号：WO1981000161A1

公开(公告)日：1981-01-22

申请号：PCT/US1980000820

申请日：1980-06-27

Applicant: NCR CORP

Inventor： NCR CORP ,  DAVISON A ,  LEWIS W

IPC: G06F13/00

CPC classification number: G06F12/04 ,  G06F11/1056 ,  G06F13/16

Abstract: A memory system (10) having a word-addressable memory (12, 14) and bit changing circuitry (35) for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory (12) and a copy memory (14). The copy memory (14) stores duplicates of the data words stored in the primary memory (12). The bit changing circuitry (35) receives a word having a bit to be changed from the copy memory (14) and returns the word, including the changed bit, to both the primary memory (12) and copy memory (14). The memory system may constitute a parity memory system in a data processor.

公开(公告)号：WO1980000626A1

公开(公告)日：1980-04-03

申请号：PCT/US1979000669

申请日：1979-08-27

Applicant: NCR CORP

Inventor： NCR CORP ,  LEWIS W ,  WARD W

IPC: G06F11/12

CPC classification number: H03M13/19

Abstract: A data processing system (10) implemented in LSI includes a plurality of identical error detection and correction (EDC) circuits (30a-f) operating either in an error correction code (ECC) mode by generating ECC parity bits, or a byte parity mode by generating or checking byte parity bits. In operation in an ECC mode, the EDC circuit (30a) generates ECC check bits for storage in association with a data word being stored in a memory (14). When a data word is fetched from the memory (14) the fetched check bits are compared with check bits generated by the EDC circuit (30a) in an error control circuit (36) to provide syndrome bits. For a single error the syndrome bits cause the provision of an enable signal to that one of a plurality of memory interface circuits (13a-d) containing the error, all the interface circuits (13a-d) being provided with identical syndrome bits identifying a bit position within the interface circuit. The EDC circuits (30) may be used individually with a 32 bit data bus or may be combined for use with a 64 bit data bus.