公开(公告)号：WO1982002275A1

公开(公告)日：1982-07-08

申请号：PCT/US1981001762

申请日：1981-12-28

Applicant: NCR CORP

Inventor： NCR CORP ,  LOCKWOOD GEORGE CORBIN ,  TRUDEL MURRAY LAWRENCE

IPC: G11C07/00

CPC classification number: G11C16/10 ,  G11C16/04 ,  G11C16/12 ,  H01L29/792 ,  H03K19/17712

Abstract: Une cellule de memoire programmable a trois portes comprend un element de memoire a seuil variable (Q2) entre deux elements de portes d'acces (Q1, Q3), formant ensemble un circuit en serie dont l'etat conducteur peut etre modifie par n'importe lequel des elements en serie. Chaque cellule possede des lignes (VW, VM, VR) pour avoir acces individuellement aux trois electrodes de portes, en plus des connexions de lignes (VB, VS) aux extremites opposees du circuit conducteur forme par les elements en serie. L'independance electrique de la ligne de memoire (VM), isole effectivement les hautes tensions associees a l'effacement et a l'ecriture de l'element de memoire (Q2) des signaux logiques de basse tension sur les autres lignes. Dans une forme de realisation, un transistor de seuil modifiable (Q2) est connecte en serie entre deux transistors a effet de champ (Q1, Q3), l'un d'eux commandant l'adressage de la cellule et l'autre actionnant le mode de lecture. La cellule est effacee avec une impulsion de haute tension sur la ligne de memoire (VM). La programmation ulterieure de la cellule est definie par les etats de tension sur les lignes de textes (VW ) et de bits (VB) du transistor d'adressage (Q1) coincidant dans le temps avec une impulsion de polarite opposee, de duree plus courte, sur la ligne de memoire (VM). Des electrodes de portes electriquement isolees (4, 6, 7) des trois transistors (Q1, Q2, Q3) commandent la conductivite du canal en segments. Les cellules peuvent etre groupees en reseau, tout en gardant l'independance de la ligne de memoire de haute tension (VM) et la flexibilite des adresses individuelles de rangees et de colonnes. L'organisation des cellules en reseaux logiques programmables est egalement decrite.

公开(公告)号：EP0041520A4

公开(公告)日：1984-03-26

申请号：EP80902382

申请日：1980-11-10

Applicant: NCR CORP

Inventor： CRAYCRAFT DONALD GREGORY ,  LOCKWOOD GEORGE CORBIN ,  DONALDSON DARRELL DOUGLAS

IPC: G11C14/00 ,  G11C11/40

CPC classification number: G11C14/00

公开(公告)号：EP0020708A4

公开(公告)日：1983-03-07

申请号：EP80900104

申请日：1980-06-03

Applicant: NCR CORP

Inventor： TRUDEL MURRAY LAWRENCE ,  LOCKWOOD GEORGE CORBIN ,  EVANS GILBERT GLENN

IPC: H01L29/78 ,  G11C11/34 ,  G11C16/04 ,  H01L21/31 ,  H01L27/10 ,  H01L29/10 ,  H01L29/792

CPC classification number: G11C16/0466 ,  H01L29/1045 ,  H01L29/792

Abstract: A low voltage write non-volatile MNOSFET memory device preferably of n-channel type has a first relatively highly doped p+ channel region (27) and a second underlying less highly doped p- region (28). The device is written to a "1" state by applying a low voltage (+12V) to the gate (21) and simultaneously applying a suitable voltage to the source (12) and/or the drain (13) to induce avalanche breakdown in the channel.

公开(公告)号：EP0025054A4

公开(公告)日：1981-10-13

申请号：EP80900585

申请日：1980-09-24

Applicant: NCR CORP

Inventor： LOCKWOOD GEORGE CORBIN

IPC: G11C11/34 ,  G11C14/00 ,  G11C17/00 ,  G11C11/40

CPC classification number: G11C14/00

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors (307, 308) coupled to the output terminals (A, B) thereof to provide backup data storage in a power-down situation The non-volatile capacitors each have a non-alterable section (307A, 308A) and an alterable section (307B, 308B), the non-alterable section having either a depletion or an enhancement threshold. The RAM cell incorporates both polysilicon resistors (305, 306) and enhancement mode devices (309, 310) in the load circuits of each cell to produce boot-strapping of the voltage on one of the multivibrator terminals (A, B) during a volatile/non-volatile write operation. A non-inverted restore of digital information to the bistable multivibrator is accomplished by simultaneous application of a step voltage to the cell power line (123A) and a restore pulse to the gate (307C, 308C) of the non-volatile capacitors. An alternative inverted restore for a cell utilizing depletion thresholds in the non-alterable sections (307A, 308A) of the non-volatile capacitors, (307, 308) involves grounding the gate electrode (307C, 308C) of the non-volatile capacitors to restore the previously written information to the multivibrator. A data processing system employing the volatile/non-volatile RAM system with a single five volt power supply (40) and a write/restore/erase signal generator (50), all implemented in five volt, n-channel silicon-insulator-silicon (SIS) device technology, is shown.

Abstract translation: 一种采用双稳态多谐振荡器的易失性/非易失性RAM单元，其具有耦合到其输出端（A，B）的非易失性可变阈值电容器（307,308），以在断电情况下提供备份数据存储。 各自具有不可变部分（307A，308A）和可变部分（307B，308B），所述不可变部分具有耗尽或增强阈值。 RAM单元在每个单元的负载电路中包括多晶硅电阻器（305,306）和增强型器件（309,310），以在一个易失性存储器中产生多谐振荡器端子（A，B）中的一个上的电压的引导 - /非易失性写入操作。 通过向单元电源线（123A）同时施加步进电压并向非易失性电容器的栅极（307C，308C）施加恢复脉冲来实现数字信息到双稳态多谐振荡器的非反向恢复。 在非易失性电容器（307,308）的不可变部分（307A，308A）中利用耗尽阈值的单元的替代反向恢复涉及将非易失性电容器的栅极电极（307C，308C）接地到 恢复先前写入多谐振荡器的信息。 采用具有单个5伏电源（40）和写入/恢复/擦除信号发生器（50）的易失性/非易失性RAM系统的数据处理系统，全部以五伏，n沟道硅绝缘体硅 （SIS）设备技术。

公开(公告)号：EP0067872A4

公开(公告)日：1985-09-26

申请号：EP82900526

申请日：1981-12-28

Applicant: NCR CORP

Inventor： LOCKWOOD GEORGE CORBIN ,  TRUDEL MURRAY LAWRENCE

IPC: G11C14/00 ,  G11C20060101 ,  G11C7/00 ,  G11C11/40 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177

CPC classification number: G11C16/10 ,  G11C16/04 ,  G11C16/12 ,  H01L29/792 ,  H03K19/17712

公开(公告)号：EP0027450A4

公开(公告)日：1982-01-08

申请号：EP80900622

申请日：1980-09-24

Applicant: NCR CORP

Inventor： LOCKWOOD GEORGE CORBIN

IPC: G11C11/34 ,  G11C5/00 ,  G11C5/14 ,  G11C11/24 ,  G11C14/00 ,  G11C16/04 ,  H02M3/07 ,  H02M7/537 ,  H03K5/02 ,  H03L5/00

CPC classification number: H02M3/07 ,  G11C5/00 ,  G11C5/145 ,  G11C14/00 ,  G11C16/0466

Abstract: A signal generator (50A) for producing, from a low voltage power supply, relatively large magnitude pulse signals of opposite polarity to a device (10) input terminal having a parallel resistor (11)-capacitor (12) circuit connection to a reference voltage is disclosed. A voltage multiplier (52) powered by the low voltage power supply provides a multiplied voltage output which is stored on a first large capacitor (58). A second large capacitor (59) has one terminal connected to the device (10) input terminal. To produce the large, opposite polarity signals, a control circuit means operates in conjunction with the voltage multiplier (52) and the first capacitor (58) to produce a predetermined sequence of voltages on the second terminal of the second capacitor (59).

公开(公告)号：AU8083982A

公开(公告)日：1982-07-20

申请号：AU8083982

申请日：1981-12-28

Applicant: NCR CORP

Inventor： LOCKWOOD GEORGE CORBIN ,  TRUDEL MURRAY LAWRENCE

IPC: G11C14/00 ,  G11C20060101 ,  G11C7/00 ,  G11C11/40 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177

Abstract: A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.