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公开(公告)号：DE3275139D1
公开(公告)日：1987-02-19
申请号：DE3275139
申请日：1982-10-22
Applicant: NEC CORP
Inventor： IWASHITA MASAO , TENMA TSUTOMU
IPC: G06F9/44
Abstract: A data processing machine for high speed processing especially of programs involving repeated executions of operational steps is disclosed, which comprises: A first memory for storing destination addresses of data; a second memory being accessed with the destination addresses output from said first memory and storing instructions therein; a third memory for receiving the data and holding it therein temporarily; a fourth memory allowing the data sent from said third memory to wait for another; an arithmetic means executing arithmetic operation in accordance with the instructions read out from said second memory; a bus for coupling said first memory, second memory, third memory, fourth memory and said arithmetic means into a ring shape; and a means for storing the destination addresses and the instruction transferred from the outside into said first and second memories, respectively. By this structure the arithmetic means and the first to fourth memories are formed in a pipe line mode, the instructions input through the interface part are stored in the second memory, and arithmetic processing for data flowing through the ringshaped bus is executed in the arithmetic means in accordance with instructions which are fetched from the second memory. The sequence of operations in the pipe line mode can be programmably controlled in accordance with the arranged instructions in the second memory.
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公开(公告)号：JPS61255127A
公开(公告)日：1986-11-12
申请号：JP9608585
申请日：1985-05-08
Applicant: NEC CORP
Inventor： HOSHINA YUICHIRO , TENMA TSUTOMU
IPC: H03M7/46
Abstract: PURPOSE:To obtain the titled device calculating in high speed a run length from an MH code string by providing the 1st storage means storing tentatively the MH code string and the 2nd storage means storing the transit state table and the run length table so as to decrease number of times of the state transition number of times with plural-bit processing. CONSTITUTION:An image memory device 10 has an MH code string data storage area 11, the transition stage table 12, and the run length tables 13-15. A memory access controller 30 reads an MH code data and references the transition state table 12 and the run length tables 13-15 by using a formed data. Then suppose that the initial value of the transition state value is preset. Further, an -bit is fetched from the MH code string. The transition state value and the fetched MH code 8-bit are given to an arithmetic unit 20, from which the formed data is obtained. The formed data obtained in this way is used as an address to reference the transition state table 12 and the run length tables 13-15 so as to obtain the next transition state table and the run length consisting of maximum three of white run length/black run length/EOL/ERROR. The operations above are repeated to calculate the run length from the MH code string.
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公开(公告)号：JPS6128164A
公开(公告)日：1986-02-07
申请号：JP14891984
申请日：1984-07-18
Applicant: Nec Corp
Inventor： MORISHITA JO , TENMA TSUTOMU , KIMURA YOSHINORI , SHIYUDO MASAMICHI
Abstract: PURPOSE: To attain picture processing at high speed efficiently by providing an information processor coping with flexibly a change in a processing algorithm and executing parallel processing and an information processor assisting the processing and executing independently sequential processing.
CONSTITUTION: A PSU monitor of the 2nd information processor PSU20 starts a task A60 to the 1st information processor IPU10, an object program is read from a data storage device IM30 and loaded sequentially to internal memories IPP11-1, 11-2...11-n of the IPU10. When the load is finished, the IPU10 attains automatic processing by using the start data added at the end of the object program. When the processing is finished, the IPU10 informs the end of processing to the PSU20. Then the PSU20 starts a task B61 to the IPU10 and a task B62 to the PSU20, the IPU10 and the PSU20 access the IM30 and attain processing entirely independently. Both tasks are executed in parallel asynchronously and when they are finished, it is informed to the PSU20 and then a task D63 is started.
COPYRIGHT: (C)1986,JPO&JapioAbstract translation: 目的：通过提供能够灵活应对处理算法变化并执行并行处理的信息处理器以及辅助处理和执行独立顺序处理的信息处理器，高效率地实现图像处理。 构成：第二信息处理器PSU20的PSU监视器向第一信息处理器IPU10启动任务A60，从数据存储装置IM30读取对象程序，并依次加载到内部存储器IPP11-1,11-2 ... 11 在IPU10。 负载完成后，IPU10通过使用在目标程序结束时添加的起始数据进行自动处理。 处理完成后，IPU10向PSU20通知处理结束。 然后，PSU20启动到IPU10的任务B61，到PSU20的任务B62，IPU10和PSU20访问IM30，完全独立地进行处理。 两个任务都是异步并行执行的，当它们完成时，它被通知给PSU20，然后任务D63被启动。
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公开(公告)号：JPS6258381A
公开(公告)日：1987-03-14
申请号：JP19999185
申请日：1985-09-09
Applicant: NEC CORP
Inventor： TENMA TSUTOMU
Abstract: PURPOSE:To attain the 4-coupled processing in parallel and in a pipeline by extracting the gathering of picture elements that can undergo the independent 8-coupled processing and producing the addresses of those picture element at a high speed. CONSTITUTION:In a 4-coupled processing mode, '0' is given so that no lebel value is given when the picture element value is equal to '0'. Then the new lebel value is given in case the upper left, upper, upper right and left picture elements all have no lavel value, i.e., are equal to '0' when the picture element value is equal to '1'. When the lebel value of at least one picture element is given, the minimum lebel value is given as the picture element value. Here the minimum label value is written to an address of the corresponding lebel value other than the minimum one of a conversion table (figure c). A figure (b) shows an auxiliary label picture and a desired label picture (figure d) is obtained from the table (figure c).
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公开(公告)号：JPS61199130A
公开(公告)日：1986-09-03
申请号：JP4049085
申请日：1985-03-01
Applicant: NEC CORP
Inventor： TENMA TSUTOMU
Abstract: PURPOSE:To execute efficiently even programs requiring the synchronous control of processings of data arrays, by providing a data flow processor with a data flow counting circuit. CONSTITUTION:When a data flow counting instruction is operated, 5 address data of picture elements a41-a45 are generated as a data array A by a program. This instruction has first value '0' as the state, and address data of picture elements a41-a45 are outputted as a data array C as it is when these data arrive successively, and the internal state value is counted up successively by one. When data of the leveling processing result of picture elements a41-a45 comes as a data array B, the data flow counting instruction outputs the data array B as a data array D as it is, and the internal state value is counted down successively by one. When 5 data arrays A come and 5 data arrays B come late, the internal state value is returned to 0, and the data flow counting instruction outputs control data E. Thus data E is used as synchronous data which generates address data of picture elements a51-a56.
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Patent Agency Ranking
公开(公告)号：JPS6261183A
公开(公告)日：1987-03-17
申请号：JP20236485
申请日：1985-09-11
Applicant: NEC CORP
Inventor： TENMA TSUTOMU
Abstract: PURPOSE:To obtain a leveling image within a short period by applying parallel processing or pipe-line processing to the leveling processing of a binary image. CONSTITUTION:Binary images consisting of NXM images are stored in a memory 1 and an address generating part 2 generates addresses (i+1-j, j) for j=1-i every each i=1-min (N, M). A 4-coupling processing circuits 30-39 read out three picture elements from the memory 1 on the basis of three addresses (x, y), (x-1, y), (x, y-1) based upon the inputted address (x, y) to execute 4-coupling processing. Then, the address generating part 2 generates addresses (i+1-j, j) for j-i+1-NXM every i=max(N, M)+1-1N+M-1 and applied the generated addresses to the circuits 30-39. The circuits 30-39 execute the same processing as said case to form an auxiliary level image and a conversion table. Different new level values required from the circuits 30-39 are used individually for the circuits 30-39 to attain the 4-coupling processing in parallel.
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公开(公告)号：JPS6433635A
公开(公告)日：1989-02-03
申请号：JP18984587
申请日：1987-07-29
Applicant: NEC CORP
Inventor： UCHIDA KAORU , TENMA TSUTOMU
Abstract: PURPOSE:To realize the high-speed working of a data flow processor by performing the convolution processing just with a fact that N pieces of tokens to be processed make a round of an internal ring. CONSTITUTION:A link table 11, an operand fetch table 12, a data memory 13, a function table 14, a buffer queue 15, and a processing unit 16 are successively connected together in a ring form via a pipeline type bus. The tokens are transferred along said internal ring bus synchronously with the pipeline clock of a data flow processor 1. When the convolution is carried out with N pieces of data, it is possible to fetch a coefficient w(i) via the table 14 by means of a group identifier of the group tokens. Thus it is not required to make a token train produced by a token producing part 20 make two rounds of the ring bus for fetching N pieces of data and the coefficient w(i). Thus the convolution processing is performed at high speed.
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公开(公告)号：JPS61243572A
公开(公告)日：1986-10-29
申请号：JP8583585
申请日：1985-04-22
Applicant: NEC CORP
Inventor： TENMA TSUTOMU
Abstract: PURPOSE:To reduce processing steps for transposing a binary picture and to shorten the processing time by executing the prescribed reading and a storage operation when the binary picture of NXN is stored by N-number of words in memory accessibly by the word unit composed of N=2 bits. CONSTITUTION:The binary picture of 16X16(=NXN) is stored up to 16 words, and 16 horizontal picture elements corresponding to one picture are stored in each picture screen. At the 1st stage (ST) pairing word addresses zero- numbered word, the eighth word - are stored at eight pairs of addresses, and the partial replacement of corresponding words is executed with respect to doubled data. At the 1st ST the corresponding words are replaced by a mask (a) made of 16 bits (1111111100000000), given j=3. The address of pairing words can be obtained at (2 +1)(X)(-2 ) and (2 +i)(+)2 , given j=3, i=0, 1, ...7, where a negative mark expresses logical denial. At the 1st-4 Sts iteration of each (j) and (i) is carried out in the same manner where an output operation j=0-n-1 and a storage operation i=0, 1-N/2-1 are given, thereby obtaining a transposed picture.
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公开(公告)号：JPS61165137A
公开(公告)日：1986-07-25
申请号：JP608885
申请日：1985-01-17
Applicant: NEC CORP
Inventor： TENMA TSUTOMU
Abstract: PURPOSE:To improve the speed performance of a processing by executing an operation processing in parallel, when outputting a data to an external bus. CONSTITUTION:When transferring a data to an output data cue memory 7 from a data memory 4, the contents of the data memory 4 are transferred temporarily to a cue memory 5, too, the data is transferred to a processor unit 6, and a data processing is executed in parallel by the processor unit, too, so that an idle time is not generated in the processing of the processor unit 6.
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公开(公告)号：JPS59195747A
公开(公告)日：1984-11-06
申请号：JP7105883
申请日：1983-04-22
Applicant: Nec Corp
Inventor： TENMA TSUTOMU
Abstract: PURPOSE: To control automatically the data input, which exceeds the capacity of hardware, to a processor with hardware by arranging operation processing parts into a ring and connecting them with a ring bus to perform parallel processings.
CONSTITUTION: Data is supplied from an input-side data bus 11 to an input part 100. The input part 100 checks a module signal and a flag signal of input data and transfers a signal for processing and a variable name data value to an operation data bus 12. The signal for processing, a bus signal, and input data are transferred to an output control part 300 through a data line 13. Processing data is inputted from an operation result data bus 14, and flag and module signals and the variable name are given in a destination control part 200, and they are transferred to the control part 300 through a data line 15. The control part 300 outputs input data itself from the data line 13, converted data, or data from the destination control part 200 to an output-side data bus 16.
COPYRIGHT: (C)1984,JPO&JapioAbstract translation: 目的：通过将操作处理部件布置在环中并将其与环形总线连接以执行并行处理，自动控制超过硬件容量的数据输入到具有硬件的处理器。 构成：从输入侧数据总线11向输入部100提供数据。输入部100检查输入数据的模块信号和标志信号，并将处理用信号和变量名数据值传送到操作数据 总线12.用于处理的信号，总线信号和输入数据通过数据线13传送到输出控制部件300.处理数据从操作结果数据总线14输入，标志和模块信号以及变量名称 在目的地控制部分200中给出，并且它们通过数据线15被传送到控制部分300.控制部分300将来自数据线13的自身的输入数据，转换的数据或从目的地控制部分200的数据输出到 输出侧数据总线16。
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