公开(公告)号：EP2746799A1

公开(公告)日：2014-06-25

申请号：EP12198395.1

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Zieren, Victor ,  Heringa, Anco ,  Wunnicke, Olaf ,  Slotboom, Jan ,  van Veldhoven, Robert ,  Claes, Jan

IPC: G01R33/06 ,  H01L29/82

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

Abstract: A semiconductor magnetic field sensor includes a semiconductor well (PW) on top of a semiconductor layer (Pepi). An insulation layer (ISO2) is located between the semiconductor layer (Pepi) and the substrate (SUB). The semiconductor well (PW) contains a lateral NPN bipolar magnetotransistor having two base contact regions (5) and (10) contacting the semiconductor well (PW). The semiconductor well (PW) further comprises two heavily n-type doped regions acting as collector regions (20) and (25) for the lateral NPN bipolar magnetotransistor. The semiconductor well (PW) further comprises a heavily doped n-type region acting as an emitter region (15) for the lateral NPN bipolar magnetotransistor and placed in between the two collector regions (20) and (25). A first MOS structure, having a first gate terminal (G 1 ), is located between the first collector region (20) and the emitter region (15). A second MOS structure, having a second gate terminal (G 2 ), is located between the emitter region (15) and the second collector region (25). By having the emitter region (15) placed between the first and the second collector regions (20) and (25), and by having properly biased MOS structures between the emitter region (15) and the collector regions (20) and (25), a first and a second collector current flowing in the semiconductor well (PW) generated during operation of the semiconductor magnetic field sensor are deflected down in a perpendicular direction from a plane defined by a surface (S) of the semiconductor magnetic field sensor and parallel to a direction of the magnetic field (B x ). The increase of the effective vertical deflection (L eff ) of the collector currents enhances the response of the semiconductor magnetic field sensor to an applied magnetic field (B x ) for a given emitter input bias current thus sensing with better accuracy also small values of the applied magnetic field (B x ). Furthermore the use of MOS structures ensures clean interfaces between the emitter region (15), the collector regions (20) and (25) and the MOS structures, avoiding the formation of material imperfections, defects, or interface states that cause an imbalance in the first and the second collector currents even in absence of a magnetic field (B x ).

Abstract translation: 半导体磁场传感器包括在半导体层（Pepi）顶部的半导体阱（PW）。 绝缘层（ISO2）位于半导体层（Pepi）和衬底（SUB）之间。 半导体阱（PW）包含具有与半导体阱（PW）接触的两个基极接触区域（5）和（10）的侧向NPN双极性磁电晶体管。 半导体阱（PW）还包括用作横向NPN双极型磁晶体管的集电极区域（20）和（25）的两个重的n型掺杂区域。 半导体阱（PW）还包括用作横向NPN双极型磁电晶体管的发射极区域（15）的重掺杂n型区域，并放置在两个集电极区域（20）和（25）之间。 具有第一栅极端子（G 1）的第一MOS结构位于第一集电极区域（20）和发射极区域（15）之间。 具有第二栅极端子（G 2）的第二MOS结构位于发射极区域（15）和第二集电极区域（25）之间。 通过使发射极区域（15）放置在第一和第二集电极区域（20）和（25）之间，并且通过在发射极区域（15）和集电极区域（20）和（25）之间具有适当偏置的MOS结构， 在半导体磁场传感器的工作过程中产生的在半导体阱（PW）中流动的第一和第二集电极电流从由半导体磁场传感器的表面（S）限定的平面沿垂直方向向下偏转并且平行 朝向磁场（B x）的方向。 集电极电流的有效垂直偏转（L eff）的增加增强了半导体磁场传感器对给定发射极输入偏置电流的施加磁场（B x）的响应，从而以更好的精度检测到较小的值 施加磁场（B x）。 此外，使用MOS结构确保发射极区域（15），集电极区域（20）和（25）与MOS结构之间的清洁界面，避免形成导致不平衡的材料缺陷，缺陷或界面状态 第一和第二集电极电流即使没有磁场（B x）。

公开(公告)号：EP2746799B1

公开(公告)日：2016-04-20

申请号：EP12198395.1

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Zieren, Victor ,  Heringa, Anco ,  Wunnicke, Olaf ,  Slotboom, Jan ,  van Veldhoven, Robert ,  Claes, Jan

IPC: G01R33/06 ,  H01L29/82 ,  H01L43/06

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

公开(公告)号：EP3001457A1

公开(公告)日：2016-03-30

申请号：EP15186224.0

申请日：2015-09-22

Applicant: NXP B.V.

Inventor： Huitsing, Albert Jan ,  Claes, Jan

IPC: H01L27/02 ,  H01L29/417

CPC classification number: H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

Abstract translation: 公开了一种PNP ESD集成电路，包括衬底，形成在衬底内的有源区，有源区包括至少一个第二导电类型的基区，多个第一导电类型的集电区形成在有源区内 ，形成在所述有源区域内的多个第一导电类型的发射极区域以及接触所述多个发射极区域和所述多个集电极区域的局部互连层（LIL），所述LIL包括形成在所述集电极区域上的冷却鳍状触点， 提升收集区域的当前处理能力。