公开(公告)号：EP2608268A1

公开(公告)日：2013-06-26

申请号：EP11194254.6

申请日：2011-12-19

Applicant: NXP B.V. ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mueller, Markus ,  Heringa, Anco

IPC: H01L29/778 ,  H01L29/872 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/1054 ,  H01L21/02104 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/872

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an AlGaN layer on a GaN layer. The device also includes first contact and a second contact. The average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact.

Abstract translation: 一种半导体器件及其制造方法。 该器件包括在GaN层上具有AlGaN层的半导体衬底。 该装置还包括第一触点和第二触点。 为了调制第一触点和第二触点之间的GaN层中的电子气的密度，AlGaN层的平均厚度在第一触点和第二触点之间变化。

公开(公告)号：EP2879182B1

公开(公告)日：2018-07-11

申请号：EP13194868.9

申请日：2013-11-28

Applicant: NXP B.V.

Inventor： Dinh, Viet Thanh ,  Vanhoucke, Tony ,  Gridelet, Evelyne ,  Heringa, Anco ,  Slotboom, Jan Willem ,  Klaassen, Dirk

IPC: H01L29/737 ,  H01L29/732 ,  H01L29/735 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7371 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/735 ,  H01L29/7378 ,  H01L29/7809 ,  H01L29/7835

Abstract: Disclosed is a transistor (100, 200, 300) having a first region (120, 320) of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region (140, 340) of the first conductivity type having a portion (142, 342) including a contact terminal (145, 345) for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region (130, 330) of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate (110) having a doped region (112) of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal (115) connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

公开(公告)号：EP2746799B1

公开(公告)日：2016-04-20

申请号：EP12198395.1

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Zieren, Victor ,  Heringa, Anco ,  Wunnicke, Olaf ,  Slotboom, Jan ,  van Veldhoven, Robert ,  Claes, Jan

IPC: G01R33/06 ,  H01L29/82 ,  H01L43/06

CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

公开(公告)号：EP2919272B1

公开(公告)日：2020-05-27

申请号：EP14159267.5

申请日：2014-03-12

Applicant: NXP B.V.

Inventor： Donkers, Johannes ,  Dinh, Viet Thanh ,  Vanhoucke, Tony ,  Gridelet, Evelyne ,  Heringa, Anco ,  Klaassen, Dirk

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/40

公开(公告)号：EP2983210A1

公开(公告)日：2016-02-10

申请号：EP14179923.9

申请日：2014-08-05

Applicant: NXP B.V.

Inventor： Heringa, Anco ,  Hijzen, Erwin ,  Surdeanu, Radu

IPC: H01L29/78

CPC classification number: H03K5/2472 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H03K17/6871 ,  H01L2924/00

Abstract: A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

Abstract translation: 一种半导体器件，包括：衬底，具有：第一端子区; 第二终端区域; 从第一端子区域朝向第二端子区域延伸的第一延伸区域; 从第二端子区域朝向第一端子区域延伸的第二延伸区域; 在第一和第二延伸区域之间的沟道区域; 栅极导体，覆盖所述衬底的所述沟道区域，所述栅极导体被配置为控制所述沟道区域中的导电; 第一控制导体，所述第一控制导体覆盖所述第一扩展区域的至少一部分，所述第一控制导体被配置为控制所述第一扩展区域中的导电; 以及覆盖第二延伸区域的至少一部分的第二控制导体，第二控制导体被配置成控制第二延伸区域中的导电，其中第一和第二控制导体在半导体器件内与栅极导体电隔离。

公开(公告)号：EP2955754A1

公开(公告)日：2015-12-16

申请号：EP14171663.9

申请日：2014-06-09

Applicant: NXP B.V.

Inventor： Steeneken, Peter ,  Heringa, Anco ,  Surdeanu, Radu ,  Van Dijk, Luc ,  Bergveld, Hendrik Johannes

IPC: H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/4238 ,  H02M3/00 ,  H02M5/00 ,  H02M7/537 ,  H03K17/687

Abstract: Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.

Abstract translation: 本公开的方面涉及包括第一半导体材料的至少两个区域和交替交错的至少两个第二半导体材料区域的装置，方法和系统。 此外，装置，方法和系统包括可以同时作为源极和漏极操作的第一电极和第二电极。 装置，方法和系统还包括在第一半导体材料上具有多个部分的第一栅极电极和在第二半导体材料上具有双向控制第一电极和第二电极之间的电流的第二栅电极。

公开(公告)号：EP2469289B1

公开(公告)日：2013-07-10

申请号：EP11194304.9

申请日：2011-12-19

Applicant: NXP B.V.

Inventor： Curatola, Gilberto ,  Zieren, Victor ,  Heringa, Anco

IPC: G01R33/06 ,  H01L27/22

CPC classification number: G01R33/06 ,  G01R33/066 ,  H01L27/22 ,  H01L29/82 ,  H01L43/00

公开(公告)号：EP2955754B1

公开(公告)日：2019-05-29

申请号：EP14171663.9

申请日：2014-06-09

Applicant: NXP B.V.

Inventor： Steeneken, Peter ,  Heringa, Anco ,  Surdeanu, Radu ,  Van Dijk, Luc ,  Bergveld, Hendrik Johannes

IPC: H01L29/06 ,  H01L29/423

公开(公告)号：EP2871672B1

公开(公告)日：2018-09-26

申请号：EP13191727.0

申请日：2013-11-06

Applicant: NXP B.V.

Inventor： Yan, Liang ,  Daamen, Roel ,  Heringa, Anco ,  Hijzen, Erwin

IPC: H01L23/367 ,  H01L27/02 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H05K7/20

CPC classification number: H01L27/1203 ,  H01L23/3677 ,  H01L27/0211 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7824 ,  H01L2924/0002 ,  H05K7/20 ,  H01L2924/00

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

公开(公告)号：EP2919272A1

公开(公告)日：2015-09-16

申请号：EP14159267.5

申请日：2014-03-12

Applicant: NXP B.V.

Inventor： Donkers, Johannes ,  Dinh, Viet Thanh ,  Vanhoucke, Tony ,  Gridelet, Evelyne ,  Heringa, Anco ,  Klaassen, Dirk

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/40

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/205 ,  H01L29/407 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378

Abstract: The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.

Abstract translation: 本公开涉及双极晶体管器件及其制造方法。 该器件包括在与所述有源区的基极 - 集电极结相邻的隔离区中的场板。 隔离区域包括栅极端子，被布置为独立于所述晶体管的集电极，基极或发射极端子被偏置。