公开(公告)号：WO2008029361A1

公开(公告)日：2008-03-13

申请号：PCT/IB2007/053579

申请日：2007-09-05

Applicant: NXP B.V. ,  ROEST, Aarnoud ,  KLEE, Mareike ,  MAUCZOK, Ruediger ,  JOEHREN, Michael

Inventor： ROEST, Aarnoud ,  KLEE, Mareike ,  MAUCZOK, Ruediger ,  JOEHREN, Michael

IPC: H01L27/02 ,  H01L21/02

CPC classification number: H01L27/0251 ,  H01L28/55 ,  H01L28/65

Abstract: The integrated circuit comprises an input structure and an output structure, which input structure comprises an input for receiving said an analog signal with an input voltage, an ESD protection element and a passband filter and which output structure comprises a first and second parallel channel so as to be differential, each channel comprising a coupling capacitor and an output for transmitting the filtered analog signal with an output voltage lower than a prescribed limit. The coupling capacitors are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially symmetric around a maximum capacitance, and being substantially independent of application of transient peak bias voltages and wherein the input voltage as amended by the input structure acts as the bias voltage.

Abstract translation: 集成电路包括输入结构和输出结构，该输入结构包括用于接收具有输入电压的模拟信号的输入端，ESD保护元件和通带滤波器，并且该输出结构包括第一和第二并行通道，以便 为了差分，每个通道包括耦合电容器和用于以低于规定极限的输出电压发送经滤波的模拟信号的输出。 耦合电容器是具有取决于偏置电压的电容的铁电电容器，所述电压依赖性围绕最大电容基本上对称，并且基本上与施加瞬态峰值偏置电压无关，并且其中由输入结构修改的输入电压用作 偏置电压。

公开(公告)号：WO2009144662A1

公开(公告)日：2009-12-03

申请号：PCT/IB2009/052201

申请日：2009-05-26

Applicant: NXP B.V. ,  LIU, Jin ,  ROEST, Aarnoud ,  ROOZEBOOM, Freddy ,  SHABRO, Vahid

Inventor： LIU, Jin ,  ROEST, Aarnoud ,  ROOZEBOOM, Freddy ,  SHABRO, Vahid

IPC: H01L21/02 ,  H01L21/316

CPC classification number: H01G4/33 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1254 ,  H01L21/31691 ,  H01L28/55

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high- permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance whilst being efficient in utilisation of semiconductor real estate.

Abstract translation: 公开了一种制造沟槽电容器的方法，以及由此制造的沟槽电容器。 该方法涉及使用用于溶胶 - 凝胶膜的真空浸渍方法，以促进高介电常数材料在半导体衬底的沟槽内的有效沉积，以提供具有高电容的沟槽电容器，同时有效地利用半导体 房地产。

公开(公告)号：WO2008028660A3

公开(公告)日：2008-03-13

申请号：PCT/EP2007/007784

申请日：2007-09-06

Applicant: NXP B.V. ,  ROEST, Aarnoud ,  KLEE, Mareike ,  MAUCZOK, Ruediger ,  JOEHREN, Michael

Inventor： ROEST, Aarnoud ,  KLEE, Mareike ,  MAUCZOK, Ruediger ,  JOEHREN, Michael

IPC: H01L21/02

Abstract: The present invention relates to a device comprising a semiconductor substrate layer and a capacitor with a metal bottom electrode layer, a metal top electrode layer and a lead-containing dielectric layer between the bottom and top electrode layers. A bottom lead-donating layer is arranged between the substrate layer and the bottom electrode layer, and a top lead-donating layer is arranged on top of the top electrode layer. This capacitor structure can be fabricated with a particularly high relative permittivity. The provision of the device of the first aspect of the invention is particularly useful in device applications that require capacitor structures with a high capacitance density, such as ESD protection and other filter applications.

公开(公告)号：EP2297774A1

公开(公告)日：2011-03-23

申请号：EP09754288.0

申请日：2009-05-26

Applicant: NXP B.V.

Inventor： LIU, Jin ,  ROEST, Aarnoud ,  ROOZEBOOM, Freddy ,  SHABRO, Vahid

IPC: H01L21/02 ,  H01L21/316

CPC classification number: H01G4/33 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1254 ,  H01L21/31691 ,  H01L28/55

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high- permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance whilst being efficient in utilisation of semiconductor real estate.