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    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS
    1.
    发明申请
    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS 审中-公开
    包含导电元件的扩散阻挡层的制造

    公开(公告)号：WO2008065125A1

    公开(公告)日：2008-06-05

    申请号：PCT/EP2007/062905

    申请日：2007-11-27

    Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

    Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

    IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532

    CPC classification number: H01L21/76849 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu- containing conductive element in an integrated-circuit device comprises: - providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface; - depositing a metal layer on the exposed surface of conductive element; - inducing diffusion of metal from the metal layer into a top section of the conductive element; - removing the remaining metal layer; - letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

    Abstract translation: 一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 提供具有横向插入电介质层并具有暴露表面的含Cu导电元件的衬底; - 在导电元件的暴露表面上沉积金属层; - 诱导金属从金属层扩散到导电元件的顶部; - 去除剩余的金属层; - 使导电元件的顶部中的扩散金属和第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。 选择金属层和第二组分的金属，使得该化合物形成抵抗Cu扩散的扩散阻挡层。 实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS
    2.
    发明申请
    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS 审中-公开
    在具有不同晶体取向的颗粒的含CU连接元件上形成可靠的扩散阻挡层

    公开(公告)号：WO2008107419A1

    公开(公告)日：2008-09-12

    申请号：PCT/EP2008/052565

    申请日：2008-03-03

    Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

    Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

    IPC: H01L21/768 ,  H01L21/321

    CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystalorientations, comprisesselectively incorporating Si into only a first set of crystallites withat least one first crystalorientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier- cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

    Abstract translation: 本发明涉及一种在含Cu互连元件上制造扩散阻挡帽的方法，该方法具有至少两种不同晶体取向的晶体，其包括仅将第一组晶体中的Si并入至少一种第一晶体取向中， 条件，并且随后选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，仅在第一组微晶上形成第一屏蔽帽部分，随后选择性地将Si并入仅第二组 的微晶，使用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

    CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE
    4.
    发明公开
    CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE 审中-公开
    控制碳纳米结构的在连接结构中的增长

    公开(公告)号：EP2074660A1

    公开(公告)日：2009-07-01

    申请号：EP07803015.2

    申请日：2007-08-29

    Applicant: NXP B.V. ,  ST Microelectronics Crolles 2 SAS

    Inventor： GOSSET, Laurent ,  TORRES, Joaquin

    IPC: H01L29/06 ,  H01L21/768

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/76831 ,  H01L21/76879 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2221/1094

    Abstract: An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.

    CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE
    5.
    发明申请
    CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE 审中-公开
    碳互连结构中碳纳米管生长的控制

    公开(公告)号：WO2008028851A1

    公开(公告)日：2008-03-13

    申请号：PCT/EP2007/058999

    申请日：2007-08-29

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  GOSSET, Laurent ,  TORRES, Joaquin

    Inventor： GOSSET, Laurent ,  TORRES, Joaquin

    IPC: H01L29/06 ,  H01L21/768

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/76831 ,  H01L21/76879 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2221/1094

    Abstract: An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.

    Abstract translation: 提供了衬底上的互连结构。 互连结构包括在衬底层上或上方的至少两个互连层上的导电互连元件。 在本发明的互连结构中，至少一个导电通孔将一个互连层上的第一互连元件或衬底层上的第一互连元件连接到不同互连层上的第二互连元件。 通孔在第一电介质层的通孔中延伸，并且包括含有导电圆柱形碳纳米结构的导电通孔材料。 至少一个覆盖层段到达通孔开口的横向延伸部分，并限定通孔孔，其足够小以防止碳纳米结构穿过通孔。 该结构在互连结构的制造期间增强了在高度方向上碳纳米结构生长的控制。

    CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES
    6.
    发明申请
    CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES 审中-公开
    用于集成电路设备中铜的CuSiN / SiN扩散阻挡层

    公开(公告)号：WO2008028850A1

    公开(公告)日：2008-03-13

    申请号：PCT/EP2007/058998

    申请日：2007-08-29

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

    Inventor： JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combinat ion provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate- circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.

    Abstract translation: 本发明涉及在电介质层中具有至少一个含铜特征的集成电路器件，以及布置在该特征与该介电层之间的扩散阻挡层堆叠。 本发明的集成电路器件具有扩散阻挡层堆叠，其包括在从含铜特征到电介质层的方向上具有CuSiN层和SiN层。 该层组合离子提供了有效的屏障，用于抑制从特征进入电介质层的铜扩散。 此外，CuSiN / SiN层序列提供了扩散阻挡层堆叠层和电介质层之间的改进的粘合性，从而提高了集成电路器件在操作期间的电迁移性能。 因此，与现有技术的器件相比，器件操作的可靠性和集成电路器件的寿命得到改善。 本发明还涉及一种用于制造这种集成电路器件的方法。

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